The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring its internal registers via SPI. It also allows programming the AD9517-4 clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC.

• AD9467 Evaluation Board
• ADC-FMC Interposer A

• ML605
• KC705
• VC707

The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

• ML605, KC705 or VC707 board
• AD9467-2x0EBZ board & Power supply
• ADC FMC interposer board
• Signal/Clock generator (clock input, 200MHz or 250MHz)
• Signal generator (analog input, for data capture)

• Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
• A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

• Download the gzip file and extract the sw/cf_ad9467_ebz.bit file.

If you have a Rev. A version of the FMC interposer board, please do the following modifications on the board.

• Populate R209 (0ohm) and make sure R211 is NOT populated.
• Insert (cut the traces) 33ohm resistors on U201 (UG3308) Y ports (pins 11 through 17).
• Make sure that R201 through R207 are NOT populated.

If you have a Rev. A version of the AD9467 evaluation board, please do the following modifications on the board.

• Remove R309 on pin 14 of AD9517 (U300).
• Remove R600 on pin 3 of NC7WZ16P (U601).
• Remove R601 on pin 1 of NC7WZ16P (U601).
• Remove R602 on pin 1 of NC7WZ07P (U600).

To begin make the following connections (see image below):

• Connect the AD9467-2x0EBZ board to the FMC Interposer board.
• Connect the interposer board to the FMC-HPC connector of ML605 board.
• Connect power to ML605 and the AD9467-2x0EBZ boards.
• Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
• Connect an external clock source to AD9467-2x0EBZ board's J201 SMA connector.
• Connect a signal generator to the AIN SMA J100 SMA connector.

If you have AD9467-200EBZ board setup the clock source to be 200MHz, if AD9467-250EBZ set up the clock source to be 250MHz. This quick start bit file configures the AD9467 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the ML605 and the AD9467-2x0EBZ boards.

Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9467 and AD9517, the program checks data capture on various test modes. Please note that AD9517 is powered down by default but is still accessable via SPI.

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] of the chipscope signal.

The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.

The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface.

The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

Please refer to the regmap.txt file in the pcores directory.

The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted.

The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the “capture select” bit (register 0x0a, bit 0).

There are several clock paths available on the evaluation board.

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

• VITA's FMC info
• Ask questions about the FPGA reference design