以太网时钟发生器10时钟输出ad9571数据表

　　The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices， Inc.， proven portfolio of high performance， low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector （PFD）， a precision charge pump （CP）， a low phase noise voltage controlled oscillator （VCO）， and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin， frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates. No external loop filter components are required， thus conserving valuable design time and board space. The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame chip scale package and can be operated from a single 3.3 V supply. The operating temperature range is −40°C to +85°C.