16位kSPS的CMOS模数转换器AD7722

　　The AD7722 is a complete low power， 16-bit， Σ-∆ ADC. The part operates from a 5 V supply and accepts a differential input voltage range of 0 V to +2.5 V or ±1.25 V centered around a common-mode bias. The AD7722 provides 16-bit performance for input bandwidths up to 90.625 kHz. The part provides data at an output word rate of 195.3 kHz. The analog input is continuously sampled by an analog modulator， eliminating the need for external sample-and-hold circuitry. The modulator output is processed by two finite impulse response （FIR） digital filters in series. The on-chip filtering reduces the external antialias requirements to first order， in most cases. The group delay for the filter is 215.5 µs， while the settling time for a step input is 431 µs. The sample rate， filter corner frequency， and output word rate are set by an external clock that is nominally 12.5 MHz. Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured on-chip by calibration. This calibration procedure minimizes the zeroscale and full-scale errors.