s70fl01gs 1gbit（128字节）3.0v SPI Flash

　　CMOS 3.0V Core  Serial Peripheral Interface （SPI） with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate （DDR） option – Extended Addressing： 32-bit address – Serial Command set and footprint compatible with S25FL-A， S25FL-K， and S25FL-P SPI families – Multi I/O Command set and footprint compatible with S25FL-P SPI family  READ Commands – Normal， Fast， Dual， Quad， Fast DDR， Dual DDR， Quad DDR – AutoBoot – power up or reset and execute a Normal or Quad read command automatically at a preselected address – Common Flash Interface （CFI） data for configuration information  Programming （1.5 Mbytes/s） – 512-byte Page Programming buffer – Quad-Input Page Programming （QPP） for slow clock systems  Erase （0.5 Mbytes/s） – Uniform 256-kbyte sectors  Cycling Endurance – 100，000 Program-Erase Cycles， minimum  Data Retention – 20 Year Data Retention， minimum.