内存高效串行LDPC码译码器架构

Recently, a number of LDPC decoder architectures have
been proposed [3]- [8]. These architectures have implemented
the widely used Sum Product Algorithm with various approaches
to satisfy throughput and hardware requirements. The
need for large hardware resources is a significant problem
in the implementation of an LDPC decoder. Mostly, serial
architectures that require lesser hardware than parallel implementations
are used. In [4] and [5] a memory efficient turbo
decoding algorithm for LDPC codes is proposed. In [11] the
issues relating to the implementation of a min-sum LDPC decoder
is explored. In [2] an offset min-sum algorithm offering
tradeoff between performance and complexity is explored to
save extrinsic message memory. In [1] an approximate min
constraint for check node update is proposed. The approximation
is exploited by the decoder to reduce hardware for check
node computation units without any noticeable degradation
in bit error rate performance. We observe that the bulk of
hardware requirement for the serial LDPC decoder lies in
the memory used for storing the extrinsic values(check to
bit or bit to check) and hence attempt to reduce it. The
proposed modification to the SPA explained in section III
is identical to the one proposed in [1] but we implement
the approximation in log-tanh domain to facilitate our serial
decoder architecture. The proposed decoder stores only few
bit to check messages which is very efficient when compared
to architectures proposed in [6], [7] which store all the bit
to check messages and also check to bit messages. When
compared to the serial decoder [2] our design stores
lesser number of extrinsic values and requires lesser memory
to store intermediate partial sums. The proposed decoder is
explained in section IV.