System on a chip Verfication-M

Prakash Rashinkar has over 15 years experience in system design and verification
of embedded systems for communication satellites, launch vehicles and spacecraft
ground systems, high-performance computing, switching, multimedia, and wireless
applications. Prakash graduated with an MSEE from Regional Engineering College,
Warangal, in India. He lead the team that was responsible for delivering the
methodologies for SOC verification at Cadence Design Systems. Prakash is an
active member of the VSIA Functional Verification DWG. He is currently Architect
in the Vertical Markets and Design Environments Group at Cadence.
Peter Paterson has over 20 years experience in ASIC and computer systems design.
Peter graduated with a BSEE from Robert Gordon’s University in Scotland. He
lead the teams that produced the first “mainframe-on-a-chip” (SCAMP) and single
chip GaAs processor while at Unisys Corporation. These devices were early precursors
to today’s SOC devices. While at Cadence, he architected the platformbased
SOC design methodology delivered to Scottish Enterprise as part of the
ALBA project. Peter is an active member of the VSIA Functional Verification
DWG. He is currently Director of ASIC Development at Vixel Corporation.
Leena Singh has over nine years experience in ASIC design and verification for
multimedia, wireless, and process control applications. Leena graduated with a
BSEE from Punjab University, Chandigarh, in India. She was a member of the
methodology development for SOC verification at Cadence. She is currently Principal
Design Engineer, of Cadence’s Vertical Markets and Design Environments.