电子发烧友App
需要将用户逻辑和IPIF连接上，需要完成user_logic的例化
Lab4pcoresmy_axi_ip_v1_00_ahdlvhdlmy_axi_ip.vhd
1 ------------------------------------------------------------------------------
2 -- my_axi_ip.vhd - entity/architecture pair
3 ------------------------------------------------------------------------------
4 -- IMPORTANT:
5 -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6 --
7 -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8 --
9 -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10 -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11 -- OF THE USER_LOGIC ENTITY.
12 ------------------------------------------------------------------------------
13 --
14 -- ***************************************************************************
15 -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
16 -- ** **
17 -- ** Xilinx, Inc. **
18 -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
19 -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
20 -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
21 -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
22 -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
23 -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
24 -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
25 -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
26 -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
27 -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
28 -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
29 -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
30 -- ** FOR A PARTICULAR PURPOSE. **
31 -- ** **
32 -- ***************************************************************************
33 --
34 ------------------------------------------------------------------------------
35 -- Filename: my_axi_ip.vhd
36 -- Version: 1.00.a
37 -- Description: Top level design, instantiates library components and user logic.
38 -- Date: Tue Oct 09 18:28:06 2012 (by Create and Import Peripheral Wizard)
39 -- VHDL Standard: VHDL'93
40 ------------------------------------------------------------------------------
41 -- Naming Conventions:
42 -- active low signals: "*_n"
43 -- clock signals: "clk", "clk_div#", "clk_#x"
44 -- reset signals: "rst", "rst_n"
45 -- generics: "C_*"
46 -- user defined types: "*_TYPE"
47 -- state machine next state: "*_ns"
48 -- state machine current state: "*_cs"
49 -- combinatorial signals: "*_com"
50 -- pipelined or register delay signals: "*_d#"
51 -- counter signals: "*cnt*"
52 -- clock enable signals: "*_ce"
53 -- internal version of output port: "*_i"
54 -- device pins: "*_pin"
55 -- ports: "- Names begin with Uppercase"
56 -- processes: "*_PROCESS"
57 -- component instantiations: "I_<#|FUNC>"
58 ------------------------------------------------------------------------------
59
60 library ieee;
61 use ieee.std_logic_1164.all;
62 use ieee.std_logic_arith.all;
63 use ieee.std_logic_unsigned.all;
64
65 library proc_common_v3_00_a;
66 use proc_common_v3_00_a.proc_common_pkg.all;
67 use proc_common_v3_00_a.ipif_pkg.all;
68
69 library axi_lite_ipif_v1_01_a;
70 use axi_lite_ipif_v1_01_a.axi_lite_ipif;
71
72 ------------------------------------------------------------------------------
73 -- Entity section
74 ------------------------------------------------------------------------------
75 -- Definition of Generics:
76 -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
77 -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
78 -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
79 -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
80 -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
81 -- C_BASEADDR -- AXI4LITE slave: base address
82 -- C_HIGHADDR -- AXI4LITE slave: high address
83 -- C_FAMILY -- FPGA Family
84 -- C_NUM_REG -- Number of software accessible registers
85 -- C_NUM_MEM -- Number of address-ranges
86 -- C_SLV_AWIDTH -- Slave interface address bus width
87 -- C_SLV_DWIDTH -- Slave interface data bus width
88 --
89 -- Definition of Ports:
90 -- S_AXI_ACLK -- AXI4LITE slave: Clock
91 -- S_AXI_ARESETN -- AXI4LITE slave: Reset
92 -- S_AXI_AWADDR -- AXI4LITE slave: Write address
93 -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
94 -- S_AXI_WDATA -- AXI4LITE slave: Write data
95 -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
96 -- S_AXI_WVALID -- AXI4LITE slave: Write data valid
97 -- S_AXI_BREADY -- AXI4LITE slave: Response ready
98 -- S_AXI_ARADDR -- AXI4LITE slave: Read address
99 -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
100 -- S_AXI_RREADY -- AXI4LITE slave: Read data ready
101 -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
102 -- S_AXI_RDATA -- AXI4LITE slave: Read data
103 -- S_AXI_RRESP -- AXI4LITE slave: Read data response
104 -- S_AXI_RVALID -- AXI4LITE slave: Read data valid
105 -- S_AXI_WREADY -- AXI4LITE slave: Write data ready
106 -- S_AXI_BRESP -- AXI4LITE slave: Response
107 -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
108 -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
109 ------------------------------------------------------------------------------
110
111 entity my_axi_ip is
112 generic
113 (
114 -- ADD USER GENERICS BELOW THIS LINE ---------------
115 --USER generics added here
116 -- ADD USER GENERICS ABOVE THIS LINE ---------------
117
118 -- DO NOT EDIT BELOW THIS LINE ---------------------
119 -- Bus protocol parameters, do not add to or delete
120 C_S_AXI_DATA_WIDTH : integer := 32;
121 C_S_AXI_ADDR_WIDTH : integer := 32;
122 C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
123 C_USE_WSTRB : integer := 0;
124 C_DPHASE_TIMEOUT : integer := 8;
125 C_BASEADDR : std_logic_vector := X"FFFFFFFF";
126 C_HIGHADDR : std_logic_vector := X"00000000";
127 C_FAMILY : string := "virtex6";
128 C_NUM_REG : integer := 1;
129 C_NUM_MEM : integer := 1;
130 C_SLV_AWIDTH : integer := 32;
131 C_SLV_DWIDTH : integer := 32
132 -- DO NOT EDIT ABOVE THIS LINE ---------------------
133 );
134 port
135 (
136 -- ADD USER PORTS BELOW THIS LINE ------------------
137 LED : out std_logic_vector(7 downto 0);
138 -- ADD USER PORTS ABOVE THIS LINE ------------------
139
140 -- DO NOT EDIT BELOW THIS LINE ---------------------
141 -- Bus protocol ports, do not add to or delete
142 S_AXI_ACLK : in std_logic;
143 S_AXI_ARESETN : in std_logic;
144 S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
145 S_AXI_AWVALID : in std_logic;
146 S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
147 S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
148 S_AXI_WVALID : in std_logic;
149 S_AXI_BREADY : in std_logic;
150 S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
151 S_AXI_ARVALID : in std_logic;
152 S_AXI_RREADY : in std_logic;
153 S_AXI_ARREADY : out std_logic;
154 S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
155 S_AXI_RRESP : out std_logic_vector(1 downto 0);
156 S_AXI_RVALID : out std_logic;
157 S_AXI_WREADY : out std_logic;
158 S_AXI_BRESP : out std_logic_vector(1 downto 0);
159 S_AXI_BVALID : out std_logic;
160 S_AXI_AWREADY : out std_logic
161 -- DO NOT EDIT ABOVE THIS LINE ---------------------
162 );
163
164 attribute MAX_FANOUT : string;
165 attribute SIGIS : string;
166 attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
167 attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
168 attribute SIGIS of S_AXI_ACLK : signal is "Clk";
169 attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
170 end entity my_axi_ip;
171
172 ------------------------------------------------------------------------------
173 -- Architecture section
174 ------------------------------------------------------------------------------
175
176 architecture IMP of my_axi_ip is
177
178 constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
179
180 constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
181
182 constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
183 constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
184 constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
185
186 constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
187 (
188 ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
189 ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
190 );
191
192 constant USER_SLV_NUM_REG : integer := 1;
193 constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
194 constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
195
196 constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
197 (
198 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
199 );
200
201 ------------------------------------------
202 -- Index for CS/CE
203 ------------------------------------------
204 constant USER_SLV_CS_INDEX : integer := 0;
205 constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
206
207 constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
208
209 ------------------------------------------
210 -- IP Interconnect (IPIC) signal declarations
211 ------------------------------------------
212 signal ipif_Bus2IP_Clk : std_logic;
213 signal ipif_Bus2IP_Resetn : std_logic;
214 signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
215 signal ipif_Bus2IP_RNW : std_logic;
216 signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
217 signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
218 signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
219 signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
220 signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
221 signal ipif_IP2Bus_WrAck : std_logic;
222 signal ipif_IP2Bus_RdAck : std_logic;
223 signal ipif_IP2Bus_Error : std_logic;
224 signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
225 signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
226 signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
227 signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
228 signal user_IP2Bus_RdAck : std_logic;
229 signal user_IP2Bus_WrAck : std_logic;
230 signal user_IP2Bus_Error : std_logic;
231
工商网监
评论