AM1705 Sitara 处理器

描述

AM1705是一款基于ARM926EJ-S的低功耗ARM微处理器。

该设备可用于原始设备制造商（OEM））和原始设计制造商（ODM）通过完全集成的混合处理器解决方案的最大灵活性，快速将具有强大操作系统，丰富用户界面和高处理器性能的设备推向市场。

ARM926EJ -S是一个32位RISC处理器内核，可执行32位或16位指令并处理32位，16位或8位数据。核心使用流水线操作，以便处理器和内存系统的所有部分可以连续运行。

ARM内核具有协处理器15（CP15），保护模块以及数据和程序存储器管理单元（MMU）表后备缓冲区。 ARM内核具有单独的16KB指令和16 KB数据高速缓存。两个内存块都与虚拟索引虚拟标记（VIVT）进行4向关联。 ARM内核还具有8KB的RAM（向量表）和64KB的ROM。

外设集包括：具有管理数据输入/输出（MDIO）模块的10/100 Mbps以太网MAC（EMAC） ;两个I ² C总线接口;三个带有串行器和FIFO缓冲器的多通道音频串行端口（McASP）;两个64位通用定时器，每个都可配置（一个可配置为看门狗）;多达8个16引脚的通用输入/输出（GPIO），具有可编程中断/事件生成模式，与其他外设复用;三个UART接口（一个具有 RTS 和 CTS ）;三个增强型高分辨率脉冲宽度调制器（eHRPWM）外设;三个32位增强型捕获（eCAP）模块外设，可配置为3个捕获输入或3个辅助脉冲宽度调制器（APWM）输出;两个32位增强型正交编码脉冲（eQEP）外设;和2个外部存储器接口：用于较慢存储器或外设的异步和SDRAM外部存储器接口（EMIFA），以及用于SDRAM的高速存储器接口（EMIFB）。

以太网媒体访问控制器（EMAC）提供设备和网络之间的有效接口。 EMAC支持10Base-T和100Base-TX，或半双工或全双工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

I ² C，SPI和USB2.0端口允许设备轻松控制外围设备和/或与主机处理器通信。

丰富的外设集提供了控制外部外围设备和与外部处理器通信的能力。有关每个外设的详细信息，请参阅本文档后面的相关章节以及相关的外设参考指南。

该器件具有一整套用于ARM处理器的开发工具。这些工具包括C编译器和Windows®调试器接口，用于查看源代码执行情况。

特性

375- and 456-MHz ARM926EJ-S™ RISC Core
- 32-Bit and 16-Bit (Thumb®) Instructions
- Single-Cycle MAC
- ARM Jazelle® Technology
- Embedded ICE-RT™ for Real-Time Debug
ARM9 Memory Architecture
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
128KB of RAM Memory
3.3-V LVCMOS I/Os (Except for USB Interface)
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-Bit SDRAM With 128-MB Address Space
Three Configurable 16550-Type UART Modules:
- UART0 With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
- Autoflow Control Signals (CTS, RTS) on UART0 Only
Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
USB 2.0 OTG Port With Integrated PHY (USB0)
- USB 2.0 Full-Speed Client
- USB 2.0 Full- and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
Two Multichannel Audio Serial Ports (McASPs):
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, or Extended Temperature