【OK210试用体验】+Linux平台下OK210的裸机开发指南_初始化内存DDR2

linux大叔 · 2015-10-14 18:21:16

linux大叔 ( 楼主 ) 2015-10-14 18:21:16 只看该作者 8289 | 3 倒序浏览

通过查看ok210的原理图可以知道，512M的DDR2由4片64M*16组成，分别挂在DMC0与DMC1上。原理图如下：

其中一片放大的原理图如下：

初始化内存DDR2之前，是有必要认识下DDR2的基本知识，这部分内容大家上网搜下，会得到大量的内容供你们学习。
那么怎么去初始化DDR2内存呢，通过阅读数据手册知道可通过以下步骤完成初始化的工作：
1.2.1.3 DDR2
Initialization sequence for DDR2 memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic
low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock
frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value
according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC
parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT)
variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off
except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value
according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the
PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
1-5
S5PV210_UM 1 DRAM CONTROLLER
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting
the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD
calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS
command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.
大家可以根据代码是分析下流程，代码会上传到附件中。
代码中DDR2的由下面分支完成：

首先需要配置DMC的时钟，我们通过阅读DDR2的数据手册其工作时钟的频率如下：

所以我们配置DMC的工作时钟位333MHz，由下面代码实现：

时钟分配完成之后需要根据210的数据手册初始化DDR2的步骤去进行初始化工作。由于ok210的内存为512M，256M挂在DMC0,256M挂在DMC1.因此我映射内存的地址为0x30000000-0x4fffffff，而DMC0映射的地址为0x30000000-0x3fffffff，DMC1映射的地址为0x40000000-0x4fffffff。
后面大家在根据代码去分析初始化的流程。