数字集成电路(Digital Integrated Circuits A Design Perspective)经典IC设计电子书

数字集成电路(Digital Integrated Circuits A Design Perspective)经典IC设计电子书
Digital Integrated Circuits A Design Perspective
Combinational vs. Sequential Logic
Static CMOS Circuit
Static Complementary CMOS
NMOS Transistors in Series/Parallel Connection
PMOS Transistors in Series/Parallel Connection
Threshold Drops
Complementary CMOS Logic Style
Example Gate: NAND
Example Gate: NOR
Complex CMOS Gate
Constructing a Complex Gate
Throughout most of the past history of integrated circuits, on-chip interconnect wires were
considered to be second class citizens that had only to be considered in special cases or
when performing high-precision analysis. With the introduction of deep-submicron semiconductor
technologies, this picture is undergoing rapid changes. The parasitics effects
introduced by the wires display a scaling behavior that differs from the active devices such
as transistors, and tend to gain in importance as device dimensions are reduced and circuit
speed is increased. In fact, they start to dominate some of the relevant metrics of digital
integrated circuits such as speed, energy-consumption, and reliability. This situation is
aggravated by the fact that improvements in technology make the production of everlarger
die sizes economically feasible, which results in an increase in the average length of
an interconnect wire and in the associated parasitic effects. A careful and in-depth analysis
of the role and the behavior of the interconnect wire in a semiconductor technology is
therefore not only desirable, but even essential.

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