FPGA控制DDS输出调频信号时，频谱仪上只出来一个下限值（...

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

--------------------------------------------------------------------

entity Set_Data_DDS_T is

port

(

clk_ref        :in  std_logic;

P_Data     :out std_logic_vector(71 downto 0);

flag       :out std_logic_vector(1 downto 0);

ena        :out std_logic;

clr        :out std_logic;

dds_ctrl   :out std_logic;

io_update  :out std_logic;

io_rst     :out std_logic

);

end Set_Data_DDS_T;

architecture Set_Data_body of Set_Data_DDS_T is

--constant CFR1_APA       :std_logic_vector(71 downto 0) := x"00_0000_2000_0000_0000"; ---Autoclear phase accumulator

constant CFR1           :std_logic_vector(71 downto 0) := x"00_0000_0000_0000_0000";

constant CFR2_DRG_ON    :std_logic_vector(71 downto 0) := x"01_004C_0820_0000_0000"; ---Enable SYNC_CLK and DRG, no-dwell HIGH

--constant CFR2_DRG_OFF   :std_logic_vector(71 downto 0) := x"01_0040_0820_0000_0000"; ---Enable SYNC_CLK and disable DRG

constant CFR3           :std_logic_vector(71 downto 0) := x"02_1F3F_C000_0000_0000"; ---REFCLK input divider bypass  

constant DAC            :std_logic_vector(71 downto 0) := x"03_0000_00FF_0000_0000";   

constant LSRR           :std_logic_vector(71 downto 0) := x"0D_0001_0001_0000_0000"; --0X0D,FIXED, DRG rate

constant LSPR_ON        :std_logic_vector(71 downto 0) := x"0B_3355_5555_28AA_AAAB"; ---0x0B, DRG limit, freq range 152.5-192.5MHz

constant LSPR_OFF       :std_logic_vector(71 downto 0) := x"0B_0000_0000_0000_0000"; ---0x0B, no signal output   

constant LSDPR        :std_logic_vector(71 downto 0) := x"0C_0000_48D1_0000_48D1"; ---0x0C, DRG frequency step

begin

process(clk_ref)

variable count        :integer range 0 to 18000;

begin

if(clk_ref'event and clk_ref='1')then

if count<8000 then  

  count:=count+1;

---reset the i/o---

if count=5 then

           io_update<='0';

           io_rst <='0';

           dds_ctrl <='0';

        elsif count=7 then

  io_rst <='1';

elsif count=10 then

  io_rst <='0';

---Send CFR1--------------

elsif count=20 then

flag<="01";

elsif count=25 then

P_Data<=CFR1;

clr<='1';

elsif count=27 then

clr<='0';         

elsif count=30 then

ena<='1';

elsif count=130 then

ena<='0';

---Send CFR2_DRG_ON--------------

elsif count=155 then

P_Data<=CFR2_DRG_ON;

clr<='1';

elsif count=157 then

clr<='0';         

elsif count=160 then

ena<='1';

elsif count=260 then

ena<='0';

---Send CFR3--------------

elsif count=285 then

P_Data<=CFR3;

clr<='1';

elsif count=287 then

clr<='0';         

elsif count=290 then

ena<='1';

elsif count=390 then

ena<='0';

---Send DAC--------------

elsif count=415 then

P_Data<=DAC;

clr<='1';

elsif count=417 then

clr<='0';         

elsif count=420 then

ena<='1';

elsif count=520 then

ena<='0';

---Send LSPR_ON--------------

elsif count=540 then

flag<="00";

elsif count=545 then

P_Data<=LSPR_ON;

clr<='1';

elsif count=547 then

clr<='0';         

elsif count=550 then

ena<='1';

elsif count=750 then

ena<='0';

---Send LSDPR--------------

elsif count=775 then

P_Data<=LSDPR;

clr<='1';

elsif count=777 then

clr<='0';         

elsif count=780 then

ena<='1';

elsif count=980 then

ena<='0';

---Send LSRR--------------

elsif count=1000 then

flag<="01";

elsif count=1005 then

P_Data<=LSRR;

clr<='1';

elsif count=1007 then

clr<='0';         

elsif count=1010 then

ena<='1';

elsif count=1110 then

na<='0';

---Update the previous registers and start FM-----

elsif count =1114 then

io_update <='1';     --update the register from the buffer;

elsif count=1118 then

        dds_ctrl <='1';

elsif count=1126 then

io_update <='0';

elsif count=1138 then

dds_ctrl <='0';

end if;

      else

P_Data<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

count :=0;

      end if;

end if;

end process;

end Set_Data_body;

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