小弟初学VHDL，请各位大神看个程序怎么错了。。。

参考下这个
VHDL实验五 4位加减法器
1、四位全加减法器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY psubadd4 IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sub:IN STD_LOGIC;
S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Co:OUT STD_LOGIC);
END psubadd4;
ARCHITECTURE rtl OF psubadd4 IS
SIGNAL d,t:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL c:STD_LOGIC_VECTOR(4 downto 0);
BEGIN
as_add: FOR i IN 0 TO 3 GENERATE
   d(i)<=a(i) AND b(i);
   t(i)<=a(i) OR b(i);
   s(i)<=a(i) XOR b(i) XOR c(i);
END GENERATE;
c(0)<=sub;
c(1)<=d(0) OR (t(0) AND c(0));
c(2)<=d(1) OR (t(1) AND d(0)) OR (t(1) AND t(0) AND c(0));
c(3)<=d(2) OR (t(2) AND d(1)) OR (t(1) AND t(2) AND d(0)) OR (t(1) AND t(2) AND t(0) AND c(0)) ;
c(4)<=d(3) OR (t(3) AND d(2)) OR (t(3) AND t(2) AND d(1)) OR (t(1) AND t(2) AND t(3) AND d(0)) OR (t(3) AND t(2) AND t(1) AND t(0) AND c(0));
Co<=c(4);
END rtl;
2、一位半加器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY half_adder IS
PORT(A,B:IN STD_LOGIC;
S,Co:OUT STD_LOGIC);
END half_adder;
ARCHITECTURE rtl OF half_adder IS
SIGNAL C,D:STD_LOGIC;
BEGIN
C<=A OR B;
D<=A NAND B;
Co<=NOT D;
S<=C AND D;
END rtl;
3、一位全加器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS
PORT(A,B,CIN:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END full_adder;
ARCHITECTURE rtl OF full_adder IS
COMPONENT half_adder IS
PORT(A,B:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END COMPONENT;
SIGNAL PCX0S,PCX0CO,PCX1CO:STD_LOGIC;
BEGIN
UO:half_adder PORT MAP(A,B,PCX0S,PCX0CO);
U1:half_adder PORT MAP(PCX0S,CIN,S,PCX1CO);
CO<=PCX0CO OR PCX1CO;
END rtl;
4、LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY half_adder IS
PORT(a,b: IN STD_LOGIC;
    s,co: OUT STD_LOGIC);
END ENTITY half_adder;
ARCHITECTURE half1 OF half_adder IS
SIGNAL c,d:STD_LOGIC;
BEGIN
c<=a OR b;
d<=a NAND b;
co<=NOT d;
s<=c AND d;
END ARCHITECTURE half1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY subadd IS
PORT(A,B,C: IN STD_LOGIC;
SUM,CARR: OUT STD_LOGIC);
END ENTITY subadd;
ARCHITECTURE ABC OF subadd IS
COMPONENT half_adder IS
PORT(a,b:IN STD_LOGIC;
    s,co:OUT STD_LOGIC);
END COMPONENT ;
SIGNAL u0_co,u0_s,u1_co:STD_LOGIC;
BEGIN
u0:half_adder PORT MAP (A,B,u0_s,u0_co);
u1:half_adder PORT MAP (u0_s,C,SUM,u1_co);
CARR<=u0_co OR u1_co;
END ARCHITECTURE ABC;

LIBRARY IEEE;
USE_IEEE.STD_LOGIC_1164.ALL;
ENTITY subadd_4 IS
PORT(a0,b0,a1,b1,a2,b2,a3,b3: IN STD_LOGIC;
       c: IN STD_LOGIC;
    sum0,sum1,sum2,sum3: OUT STD_LOGIC_;
    carr: OUT STD_LOGIC);
END ENTITY subadd_4;
ARCHITECTURE ABC OF subadd_4 IS
COMPONENT subadder IS
   PORT(A,B,C: IN STD_LOGIC;
     SUM,CARR: OUT STD_LOGIC);
END COMPONENT;
SIGNAL C_4:STD_LOGIC_VECTOR(4 DOWNTON 0);
BEGIN
SIGNAL c1,c2,c3: IN STD_LOGIC;
s0:subadder PORT MAP(a0,b0,cin,sum0,c1);
s1:subadder PORT MAP(a1,b1,c1,sum1,c2);
s2:subadder PORT MAP(a2,b2,c2,sum2,c3);
s3:subadder PORT MAP(a3,b3,c3,sum3,carr);
END ARCHITECTURE ABC;

///////////////////////////////////////////
LIBRARY IEEE;
USE_IEEE.STD_LOGIC_1164.ALL;
ENTITY subadd4 IS
PORT(A,B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       C: IN STD_LOGIC;
     SUM: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    CARR: OUT STD_LOGIC);
END ENTITY subadd4;
ARCHITECTURE ABC OF subadd4 IS
COMPONENT subadder IS
   PORT(A,B,C: IN STD_LOGIC;
     SUM,CARR: OUT STD_LOGIC);
END COMPONENT;
SIGNAL C_4:STD_LOGIC_VECTOR(4 DOWNTON 0);
BEGIN
C_4(0)<=C;
s0:subadder PORT MAP(A(0),B(0),C_4(0),SUM(0),C_4(1));
s1:subadder PORT MAP(A(1),B(1),C_4(1),SUM(1),C_4(2));
s2:subadder PORT MAP(A(2),B(2),C_4(2),SUM(2),C_4(3));
s3:subadder PORT MAP(A(3),B(3),C_4(3),SUM(3),C_4(4));
CARR<=C_4(4);
END ARCHITECTURE ABC;