求助 三分频程序出错

初学FPGA，自己编写了一个三分频程序，有错，代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divclk3 is
    port(inclk : in std_logic;
         outclk : out std_logic);
end divclk3;

architecture one of divclk3 is
    signal tmp : std_logic;
    signal rise_cnt : std_logic_vector(1 downto 0) := "00";
    signal down_cnt : std_logic_vector(1 downto 0) := "00";
    signal cnt : std_logic_vector(1 downto 0) := "00";
begin

    process(inclk)
    begin
        if(inclk'event and inclk = '1') then
            rise_cnt <= rise_cnt + 1;
        end if;
    end process;
   
    process(inclk)
    begin
        if(inclk'event and inclk = '0') then
            down_cnt <= down_cnt + 1;
        end if;
    end process;
   
    process(rise_cnt, down_cnt)
    begin
        cnt <= rise_cnt + down_cnt;
        if(cnt="11") then
            tmp <= not tmp;
            rise_cnt <= "00";
            down_cnt <= "00";
        end if;
    end process;
    outclk <= tmp;
end one;

编译出错，提示为：
Error (10028): Can't resolve multiple constant drivers for net "rise_cnt[1]" at divclk3.vhd(19)
Error (10029): Constant driver at divclk3.vhd(31)
Error (10028): Can't resolve multiple constant drivers for net "rise_cnt[0]" at divclk3.vhd(19)
Error (10028): Can't resolve multiple constant drivers for net "down_cnt[1]" at divclk3.vhd(26)
Error (10028): Can't resolve multiple constant drivers for net "down_cnt[0]" at divclk3.vhd(26)
Error: Can't elaborate user hierarchy "divclk3:inst6"
Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 9 warnings
Error: Peak virtual memory: 240 megabytes
Error: Processing ended: Thu Nov 29 22:37:56 2012
Error: Elapsed time: 00:00:05
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 8 errors, 9 warnings

自己想了半天，实在是不知问题所在，望各位指点，感激不尽！