HAL_ETH_TransmitFrame函数无法返回2（HAL_BUSY）是什么意思？

tcp或udp长时间通信
log出现

[60094] E/drv.emac: eth transmit frame faild: 2
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)函数中
c state = HAL_ETH_TransmitFrame(&EthHandle, framelength); if (state != HAL_OK) { LOG_E("eth transmit frame faild: %d", state); }c
但是HAL_ETH_TransmitFrame函数内根本就不会返回2（HAL_BUSY），这是什么鬼

HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
uint32_t bufcount = 0U, size = 0U, i = 0U;

/ Process Locked /
__HAL_LOCK(heth);

/ Set the ETH peripheral state to BUSY /
heth->State = HAL_ETH_STATE_BUSY;

if (FrameLength == 0U)
{
/ Set ETH HAL state to READY /
heth->State = HAL_ETH_STATE_READY;

/* Process Unlocked */
__HAL_UNLOCK(heth);
return  HAL_ERROR;                                    
}

/ Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) /
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
{
/ OWN bit set /
heth->State = HAL_ETH_STATE_BUSY_TX;

/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_ERROR;
}

/ Get the number of needed Tx buffers for the current frame /
if (FrameLength > ETH_TX_BUF_SIZE)
{
bufcount = FrameLength/ETH_TX_BUF_SIZE;
if (FrameLength % ETH_TX_BUF_SIZE)
{
bufcount++;
}
}
else
{
bufcount = 1U;
}
if (bufcount == 1U)
{
/ Set LAST and FIRST segment /
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
/ Set frame size /
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
/ Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA /
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/ Point to next descriptor /
heth->TxDesc= (ETH_DMADescTypeDef )(heth->TxDesc->Buffer2NextDescAddr);
}
else
{
for (i=0U; i< bufcount; i++)
{
/ Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);

  if (i == 0U) 
  {
    /* Setting the first segment bit */
    heth->TxDesc->Status |= ETH_DMATXDESC_FS;  
  }
  /* Program size */
  heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
  if (i == (bufcount-1U))
  {
    /* Setting the last segment bit */
    heth->TxDesc->Status |= ETH_DMATXDESC_LS;
    size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
    heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
  }
  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
  heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
  /* point to next descriptor */
  heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
}

/ When Tx Buffer unavailable flag is set: clear it and resume transmission /
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
{
/ Clear TBUS ETHERNET DMA flag /
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
/ Resume DMA transmission/
(heth->Instance)->DMATPDR = 0U;
}

/ Set ETH HAL State to Ready /
heth->State = HAL_ETH_STATE_READY;

/ Process Unlocked /
__HAL_UNLOCK(heth);

/ Return function status /
return HAL_OK;
}```c