【FPGA经典试题】采用一个乘法器实现下面代码相同的功能

1. 
   
2. 
   
3. module resour_share(i_data,o_square);
   
4. parameter DATA_WIDTH = 8;
   
5. 
   
6. parameter PRO_WIDTH = 16;
   
7. input [DATA_WIDTH-1:0] i_data;
   
8. output [PRO_WIDTH-1:0] o_square;
   
9. wire [DATA_WIDTH-1:0] data_bar;
   
10. assign data_bar = ~ i_data + 1'b1;
    
11. wire [DATA_WIDTH-1:0] multi,multi_d;
    
12. assign multi = (i_data[DATA_WIDTH-1]) ? data_bar : i_data;
    
13. assign multi_d = (i_data[DATA_WIDTH-1]) ? data_bar : i_data;
    
14. mul_8bit mul(.multiplicand(multi_d),
    
15. .multiplier(multi),
    
16. .ValOut(o_square));
    
17. endmodule
    
18. module mul_8bit(multiplicand,multiplier,ValOut); //start
    
19. parameter width = 8;
    
20. //input clk;
    
21. //input reset;
    
22. //input start;
    
23. input [7:0] multiplicand;
    
24. input [7:0] multiplier;
    
25. output [15:0] ValOut;
    
26. wire [7:0] mulD;
    
27. wire [7:0] mulR;
    
28. wire sign1,sign2,sign3,sign4;
    
29. wire one1,one2,one3,one4;
    
30. wire two1,two2,two3,two4;
    
31. //·ûºÅsign=~A[2n+1] & (A[2n]|
    
32. A[2n-1])£»sign±íʾ·ûºÅ룬μ±ÆäΪ1ʱ£¬Ôò²¼Ë¹±àÂëÈ¡Õý£»·´Ö®£¬È¡¸º¡£
    
33. A[-1] ²¹Áã¼´A[-1]=0
    
34. assign sign1 = ~mulR[1] & (mulR[0] | 0);
    
35. 
    
36. assign sign2 = ~mulR[3] & (mulR[2] | mulR[1]);
    
37. assign sign3 = ~mulR[5] & (mulR[4] | mulR[3]);
    
38. assign sign4 = ~mulR[7] & (mulR[6] | mulR[5]);
    
39. //one; one=A[2n]^A[2n-1]£»Èôone=1,Ôò²¿·Ö»ýΪb£»·ñÔòΪ0¡£
    
40. assign one1 = mulR[0]^0;
    
41. assign one2 = mulR[2]^mulR[1];
    
42. assign one3 = mulR[4]^mulR[3];
    
43. assign one4 = mulR[6]^mulR[5];
    
44. //two=(¡«A[2n+1]&A[2n]&A[2n-1])|(A[2n+1]&¡«A[2n]&¡«A[2n-1])£»ÈôtwoΪ1£¬Ô
    
45. ò²¿·Ö»ýΪ2b£»·ñÔòΪ0¡£
    
46. assign two1 = (~mulR[1] & mulR[0] & 0)|(mulR[1] & ~mulR[0] & 1);
    
47. assign two2 = (~mulR[3] & mulR[2] & mulR[1])|(mulR[3] & ~mulR[2] &
    
48. ~mulR[1]);
    
49. assign two3 = (~mulR[5] & mulR[4] & mulR[3])|(mulR[5] & ~mulR[4] &
    
50. ~mulR[3]);
    
51. assign two4 = (~mulR[7] & mulR[6] & mulR[5])|(mulR[7] & ~mulR[6] &
    
52. ~mulR[5]);
    
53. //·ûºÅÀ©Õ¹
    
54. wire [15:0] temp;
    
55. assign temp = {{8{mulD[7]}},mulD[7:0]};
    
56. // ¼ÆËãÊä³ö
    
57. wire [15:0] dat_w1,dat_w2,dat_w3,dat_w4;
    
58. //- 2 * B = = (~ (B << 1)) + 1 ;2B= (B<<1);
    
59. assign dat_w1 = (two1) ? ((sign1) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
    
60. ((one1) ? ((sign1) ? temp :{~temp+1'b1} ) : 0);
    
61. assign dat_w2 = (two2) ? ((sign2) ? {temp[14:0],1'b0}: (~{temp[14:0],1'b0} + 1'b1 )) :
    
62. ((one2) ? ((sign2) ? temp :{~temp+1'b1} ) : 0);
    
63. assign dat_w3 = (two3) ? ((sign3) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
    
64. 
    
65. ((one3) ? ((sign3) ? temp :{~temp+1'b1} ) : 0);
    
66. assign dat_w4 = (two4) ? ((sign4) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
    
67. ((one4) ? ((sign4) ? temp :{~temp+1'b1}) : 0);
    
68. assign ValOut = dat_w1 + {dat_w2[13:0],2'b00} + {dat_w3[11:0],4'b0000} +
    
69. {dat_w4[9:0],6'b000000};
    
70. assign mulD = multiplicand;
    
71. assign mulR = multiplier;
    
72. endmodule

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