为什么HDL解析器164错误？

@ william25Remove进程。
这里不需要处理
评论过程，它应该工作。
阅读有关VHDL流程的更多信息
库ieee;使用ieee.std_logic_1164.all;实体iNOT isport（iA：in bit; oNa：out bit）; end; inot行为isot i***eginoNa end behave;
库ieee;使用ieee.std_logic_1164.all;实体iOR isport（iA，iB：in bit; oC：out bit）; end; ior i***eginoC end behavior的架构行为;
库ieee;使用ieee.std_logic_1164.all;实体iAND是端口（iA，iB：位; oC：out位）; end;架构行为iand i***egin
oC结束表现;
库ieee;使用ieee.std_logic_1164.all;
实体iXOR isport（iData，冒号：在bit_vector中（1 downto 0）; oResult：out bit）; end;
iXOR的架构弧是
component iOR isport（iA，iB：in bit; oC：out bit）; end component;
component iAND isport（iA，iB：in bit; oC：out bit）; end component; component iNOT isport（iA：in bit; oNa：out bit）; end component;
信号x：bit_vector（4 downto 0）;开始
--process  - 开始
U0：iNOT端口映射（iA => iData（0），oNa => x（0））;
U1：iNOTport map（iA => iData（1），oNa => x（1））; U2：iANDport map（iA => iData（0），iB => iData（1），oC => x（3）
）; U3：iANDport map（iA => x（0），iB => x（1），oC => x（4））; U4：iORport map（iA => x（4），iB => x（
3），oC => oResult）;  - 结束过程;结束弧;
-Pratham ------------------------------------------------
----------------------------------------------请注意 - 请
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
--------------------------------------------------
-----------------------
在原帖中查看解决方案



以下为原文

@william25 Remove process. There is no need of process here
 
Comment Process and it should work. Read more about VHDL Process
 
 

library ieee;
use ieee.std_logic_1164.all;
entity iNOT is
port(iA: in bit;
oNa: out bit);
end;
architecture behave of inot is
begin
oNa <= not iA;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity iOR is
port(iA, iB: in bit;
oC: out bit);
end;
architecture behave of ior is
begin
oC <= iA or iB;
end behave;

library ieee;
use ieee.std_logic_1164.all;
entity iAND is
port(iA, iB: in bit;
oC: out bit);
end;
architecture behave of iand is
begin
oC <= iA and iB;
end behave;

library ieee;
use ieee.std_logic_1164.all;
entity iXOR is
port(iData,colon :in bit_vector (1 downto 0);
oResult: out bit);
end;
architecture arc of iXOR is
component iOR is
port(iA, iB: in bit;
oC: out bit);
end component;
component iAND is
port(iA, iB: in bit;
oC: out bit);
end component;
component iNOT is
port(iA: in bit;
oNa: out bit);
end component;
signal x: bit_vector (4 downto 0);
begin
--process 
--begin
U0: iNOT
port map
(iA => iData(0),
oNa => x(0)
);

U1: iNOT
port map(
iA => iData(1),
oNa => x(1)
);
U2: iAND
port map(
iA => iData(0),
iB => iData(1),
oC => x(3)
);
U3: iAND
port map(
iA => x(0),
iB => x(1),
oC => x(4)
);
U4: iOR
port map(
iA => x(4),
iB => x(3),
oC => oResult
);
--end process;
end arc;
-Pratham

----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------View solution in original post

@ william25Remove进程。
这里不需要处理
评论过程，它应该工作。
阅读有关VHDL流程的更多信息
库ieee;使用ieee.std_logic_1164.all;实体iNOT isport（iA：in bit; oNa：out bit）; end; inot行为isot i***eginoNa end behave;
库ieee;使用ieee.std_logic_1164.all;实体iOR isport（iA，iB：in bit; oC：out bit）; end; ior i***eginoC end behavior的架构行为;
库ieee;使用ieee.std_logic_1164.all;实体iAND是端口（iA，iB：位; oC：out位）; end;架构行为iand i***egin
oC结束表现;
库ieee;使用ieee.std_logic_1164.all;
实体iXOR isport（iData，冒号：在bit_vector中（1 downto 0）; oResult：out bit）; end;
iXOR的架构弧是
component iOR isport（iA，iB：in bit; oC：out bit）; end component;
component iAND isport（iA，iB：in bit; oC：out bit）; end component; component iNOT isport（iA：in bit; oNa：out bit）; end component;
信号x：bit_vector（4 downto 0）;开始
--process  - 开始
U0：iNOT端口映射（iA => iData（0），oNa => x（0））;
U1：iNOTport map（iA => iData（1），oNa => x（1））; U2：iANDport map（iA => iData（0），iB => iData（1），oC => x（3）
）; U3：iANDport map（iA => x（0），iB => x（1），oC => x（4））; U4：iORport map（iA => x（4），iB => x（
3），oC => oResult）;  - 结束过程;结束弧;
-Pratham ------------------------------------------------
----------------------------------------------请注意 - 请
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
--------------------------------------------------
-----------------------



以下为原文

@william25 Remove process. There is no need of process here
 
Comment Process and it should work. Read more about VHDL Process
 
 

library ieee;
use ieee.std_logic_1164.all;
entity iNOT is
port(iA: in bit;
oNa: out bit);
end;
architecture behave of inot is
begin
oNa <= not iA;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity iOR is
port(iA, iB: in bit;
oC: out bit);
end;
architecture behave of ior is
begin
oC <= iA or iB;
end behave;

library ieee;
use ieee.std_logic_1164.all;
entity iAND is
port(iA, iB: in bit;
oC: out bit);
end;
architecture behave of iand is
begin
oC <= iA and iB;
end behave;

library ieee;
use ieee.std_logic_1164.all;
entity iXOR is
port(iData,colon :in bit_vector (1 downto 0);
oResult: out bit);
end;
architecture arc of iXOR is
component iOR is
port(iA, iB: in bit;
oC: out bit);
end component;
component iAND is
port(iA, iB: in bit;
oC: out bit);
end component;
component iNOT is
port(iA: in bit;
oNa: out bit);
end component;
signal x: bit_vector (4 downto 0);
begin
--process 
--begin
U0: iNOT
port map
(iA => iData(0),
oNa => x(0)
);

U1: iNOT
port map(
iA => iData(1),
oNa => x(1)
);
U2: iAND
port map(
iA => iData(0),
iB => iData(1),
oC => x(3)
);
U3: iAND
port map(
iA => x(0),
iB => x(1),
oC => x(4)
);
U4: iOR
port map(
iA => x(4),
iB => x(3),
oC => oResult
);
--end process;
end arc;
-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

谢谢，但为什么这个过程会导致这样的问题呢？



以下为原文

Thank you, but why did the process cause such issue?

嗨@ william25
Portmap只是使用（调用）已经存在的数字电路，换句话说是声明电路的输入和输出引脚。
在过程中，您只是描述声明的电路的功能或行为。
VHDL标准不允许在进程块内部进行这种端口映射。
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi @william25
Portmap is just using(calling) the already existing digital circuit in other words declaring input and output pins of a circuit. In process u r just describing the function or behavior of declared circuit.

VHDL standard doesn't allow this kind of port mapping inside process block.

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

william25写道：
谢谢，但为什么这个过程会导致这样的问题呢？
因为您无法在进程中实例化组件。
这是基本的VHDL。
----------------------------是的，我这样做是为了谋生。



以下为原文

william25 wrote:
Thank you, but why did the process cause such issue?

Because you cannot instantiate a component in a process. This is basic VHDL.
 
 
----------------------------Yes, I do this for a living.

嗨@ william25
这回答了你的疑问吗？
如果是，请通过为其他用户的利益标记解决方案来关闭该线程。
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi @william25
Did that answered your query? If yes, please close the thread by marking the solution in the interest of other users.
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.