如何利用SP605 TI_ads5282使用xapp1064进行反序列化数据配置？

你好，
我想将德州仪器ADS5282EVM（高达65MHz）与SP605评估板结合使用。
我使用Spartan 6 LX150T开发套件和Xapp 1064成功地对来自该ADC（65MHz）的数据进行反序列化。
然而，在SP605板中，用于xapp1064（更高的解串因子）的ADC的帧时钟在BANK0中以及8个数据通道中的3个。
其他数据通道位于BANK2中。
我试图修改xapp1064 vhd文件，以便使用BANK0的3个通道和BANK2的1个通道，因为我想实现一个4通道数据采集系统。
所以我在Xapp1064上又使用了一个BUFPLL来计时BANK2数据，该数据由同一个PLL驱动，后者驱动BUFPLL，用于为BANK0产生时钟和serdesstrobe信号。
我分别在BANK0和BANK2中找到BUFPLL组件。
我在Chipscope中看到的是，在我的自定义vhdl核心中，所有四个通道中的数据都是正确反序列化的。
对于用于测试目的的这种设计，我使用连接到MPMC NPI端口的自定义内核和连接到XCL MPMC端口的微型连接器。
但是，因为我想在实际设计中通过以太网在PC中发送数据，所以我也使用了Soft TEMAC。
数据成功发送到PC，但位于BANK2的第4个通道的数据不正确。
前3个频道的数据与预期一致。
我正在使用Xilinx EDK 14.3来实现设计。
有没有人在这样的配置中成功地反序列化数据（ti ads5282和Xilinx SP605）？
有没有人对这样的设计有任何推荐？
也许关于时间安排？
最好的祝福，
Lefteris



以下为原文

Hello,

I would like to combine Texas Instruments ADS5282EVM (up to 65MHz) along with SP605 evaluation board. I have succesfully deserialize data from this ADC (65MHz) using a Spartan 6 LX150T Development Kit and Xapp 1064.

However in SP605 board the framing clock from ADC which is used in xapp1064 (higher deserialization factors) is in BANK0 along with 3 out of 8 data channels. The other data channels are in BANK2.

I tried to modified xapp1064 vhd files in order to use the 3 channels from BANK0 and 1 channel from BANK2 as i want to implement a 4 channel data acquisition system. So i used one more BUFPLL in respect to Xapp1064, to clock BANK2 data, which is drived by the same PLL which drives the BUFPLL which is used to produce clock and serdesstrobe signals for BANK0. I loc BUFPLL components respectively in BANK0 and BANK2.

What i see in Chipscope is that data in all four channels are correct deserialized in my custom vhdl core. For this design which was used for test purposes, i used my custom core connected to MPMC NPI port and microblaze connected to XCL MPMC port.

However, because i want to sent data through Ethernet in a PC in the real design i used also Soft TEMAC. Data were succesfully send to the PC but data from the 4th channel located in BANK2 were not correct. Data from the first 3 channels were as expected.

I am using Xilinx EDK 14.3 for the implementation of the design.

Have anyone succesfully deserialize data in such a configuration (TI ads5282 and Xilinx SP605)?

Does anyone has any reccomendation about such a design? Maybe about the timing constaints?

Best Regards,
Lefteris