FPGA设计运行从49.875切换到41.56 MHz时PLL或DCM会产生主时钟

你好
是的，这应该适用于可变时钟和固定参数。
你可以交叉检查这是模拟。
问候，萨蒂什-----------------------------------------------
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以下为原文

Hi
 
yes this should work with the variable clocks and fixed parameters.
 
You can cross check this is simulation.
Regards,

Satish

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你好
是的，这应该适用于可变时钟和固定参数。
你可以交叉检查这是模拟。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
yes this should work with the variable clocks and fixed parameters.
 
You can cross check this is simulation.
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

目前尚不清楚你要求重置的是什么。
DCM重置处于活动状态时，DCM的输出不会切换。
即，重置DCM的状态机不得使用DCM的输出作为时钟。
重置DCM后，它应该能够重新获得新时钟频率的锁定。
您可以在IBUFG之后直接使用BUFG来驱动需要通过DCM重置生活的任何内容。
另外，根据外部时钟在重新编程时的作用，您可能需要使用单独的时钟源来编程外部部件。
我有一个使用Silabs部件的设计，需要在重新编程时关闭输出。
我没有针对该S6设计的其他时钟输入，但我使用内部振荡器（参见库指南中的STARTUP_SPARTAN6）来运行通过I2C重新编程外部器件的状态逻辑。
幸运的是，I2C不需要精确的时钟频率。
一旦时钟恢复运行，时钟振荡器域中的状态逻辑就会复位DCM / PLL以调出芯片的其余部分。
-  Gabor



以下为原文

It's not clear what you're asking about reset.  While the DCM reset is active, the DCM's outputs are not toggling.  i.e. your state machine to reset the DCM must not use the outputs of the DCM as a clock.  After resetting the DCM, it should be able to regain lock for the new clock frequency.  You can have a BUFG directly after the IBUFG to drive anything that needs to live through DCM reset.  Also depending on what your external clock does while it's being reprogrammed, you may need to use a separate clock source to do the programming of the external part.  I have a design using a Silabs part that needs to shut down the outputs while being reprogrammed.  I have no other clock inputs for that S6 design, but I use the internal oscillator (see STARTUP_SPARTAN6 in the libraries guide) to run the state logic that reprograms the external device over I2C.  Luckily I2C does not require a precise clock frequency.  Once the clock is back up and running, the state logic in the clock oscillator domain then resets the DCM / PLL to bring up the rest of the chip.
-- Gabor