在Spartan 6 - LX9上测试FPGA-Design错误问题

大家好，
在实现目标设备（Spartan 6  -  LX45）上的软件（使用ISE 14.6的VHDL）之前，我在评估板（Spartan 6  -  LX9）上测试了我的FPGA-Design。
在此转换过程中发生一个错误：
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错误：位置：1198  -  PLL时钟组件未放置在可路由站点。
PLL组件放置在现场。
相应的时钟负载组件放置在现场。
如果PLL放置在相邻的水平时钟区域中，则PLL可以使用PLL和时钟负载之间的快速路径。
您可能想要分析存在此问题的原因并进行更正。
PAR中的此放置是不可用的，因此，应在您的设计中修复此错误情况。
您可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为WARNING以生成NCD文件。
然后可以在FPGA编辑器中使用此NCD文件来调试问题。
下面列出了此时钟放置规则中使用的所有COMP.PINS的列表。
可以直接在.ucf文件中使用这些示例将此ERROR降级为警告。
错误：包装：1654  - 时序驱动的放置阶段遇到错误。
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sugested解决方案（插入NET“top_out_VIDEO_Clock”CLOCK_DEDICATED_ROUTE = FALSE;到ucf文件）工作。
但我想了解这个错误的路由原因。
之后可能会有更好的解决方案，既不会导致错误也不会导致警告。
或者我可以在将来防止这种错误。
以下是一些更多信息：时钟输入（通向XILINX ipCore-Generator的PLL实例）位于引脚L15（Bank 1，IO_L42P_GCLK7_M1UDM_1），视频时钟输出位于引脚U8 Bank 2，IO_L41P_2）。
1号银行和2号银行之间的过境问题是什么？
感谢您的帮助！



以下为原文


Hello everyone,

I testes my FPGA-Design on an evaluation board (Spartan 6 - LX9) before implementing (VHDL with ISE 14.6) the software on the destination device (Spartan 6 - LX45). One error occurs in the course of this transition:

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ERROR:Place:1198 - A PLL clock component is not placed at a routable site. The
   PLL component is placed at site .
   The corresponding clock load component is placed at
   site . The PLL can use the fast path between the PLL and the clock
   load if they are placed in adjacent horizontal clock regions. You may want to
   analyze why this problem exists and correct it. This placement is UNROUTABLE
   in PAR and therefore, this error condition should be fixed in your design.
   You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
   this message to a WARNING in order to generate an NCD file. This NCD file can
   then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS
   used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "CLOCK/pll_base_inst/PLL_ADV.CLKOUT0" CLOCK_DEDICATED_ROUTE = FALSE; >
   < NET "top_out_VIDEO_Clock" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
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The sugested solution (insert NET "top_out_VIDEO_Clock" CLOCK_DEDICATED_ROUTE = FALSE; to ucf-file) works.

But I want to understand the route cause of this error. After that there might be a better solution, leading to neither error nor warning. Or I can prevent this errors in the future.

Here are some more information: The clock-input (leading to the PLL-instance from XILINX ipCore-Generator) is on Pin L15 (Bank 1, IO_L42P_GCLK7_M1UDM_1), the video-clock-output is on Pin U8 Bank 2, IO_L41P_2). Is the crossing between Bank 1 and 2 the problem?

Thank you for your help!

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