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我在使用case语句时遇到问题....虽然我使用它如下:: -------------------------------------------------- --- 过程（CLK） 开始 如果clk'event和clk ='1'那么 情况1 读块ram data1 在case2和stop中启用第一个条件 结束案例1 案例2 在特殊操作中使用data1 在case2中启用第一个条件来读取data2，data3等并停止 结束案例2 万一; 结束过程 -------------------------------------------------- --- 当从块ram中读取data1并且第二种情况下的操作也完成时，我启用了case1中的第一个条件，并且在case2中使用最后一个条件停止case2，在模拟中，操作在两个case中完成。 但是在FPGA上只读取data1并输入第二种情况，只需一次...... 所以，任何身体都可以帮助我在他的脑海里尝试它的任何想法？ 提前致谢 以上来自于谷歌翻译 以下为原文 Hi all ... i have a problem in using case statement .... while i used it as the following :: ----------------------------------------------------- process(clk) begin if clk'event and clk = '1' then case1 read block ram data1 enable first condition in case2 and stop end case1 case2 use data1 in special operation enable first condition in case2 to read data2 ,data3 and others and stop end case2 end if; end process ----------------------------------------------------- while read data1 from block ram is done and the the operation in second case is done too , then i enabled the first condition in case1 and stop case2 by the last condition in case2 ,,, in simulation the operation is done in two case Alternately ... but on FPGA just data1 is read and entered to the second case also just once ..... so , any body can help me in any idea that in his mind to try it??? thanks in advance 
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我根本不清楚你想从你的描述和伪代码做什么。
在一个流程中是否有两个不同的case语句？ 为什么一个案例陈述（经典的FSM）不够？ 如果将两个case语句拆分为两个进程（两个进程之间有效乒乓），会发生什么？ 如果您在模拟中看到了所需的行为，但在硬件中却没有，那么在合成期间会发生一些变化。 综合报告对相关信号的评价是什么？ 问候， 霍华德 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 It isn't clear to me at all what you trying to do from your description and pseudo-code. Do you have two distinct case statements inside one process? Why is one case statement (a classic FSM) not sufficient? What happend if you split the two case statements over two processes (effectively ping-pong between the two processes)? If you see the behaviour you want in simulation but not in hardware then something has changed during synthesis. What does the synthesis report say for the relevant signals? Regards, Howard ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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在一个流程中是否有两个不同的case语句？
当然是 如果将两个case语句拆分为两个进程（两个进程之间有效乒乓），会发生什么？ 我做到了，但数据没有进入第二个过程!!!! ，我错误的同步............ 现在看，我尝试以下方法:: -------------------------------------------------- -------------------------------------------------- --- 过程1（CLK） 开始 如果clk'event和clk ='1'那么 case2 sel是 当0 => case1卖出时 当0 =>读取数据1时 当其他=> null; 结束案例1; 。 。 。 。 ////对data1 ////进行处理并将数据存储在帧缓冲区中（（通过双端口块ram的端口a）） 。 当12 => sel => 0时; /////读取data2，data3和其他数据进行处理 当其他=> null; 结束案例2; 万一; 结束过程1; process2（clk）///////这个过程在第一个进程写完时连续读取//////// 开始 如果rising_edge（clk）那么 ///////////读取存储在帧缓冲区中的数据（（通过相同的前一个双端口块ram的端口b））并将其显示在VGA端口////////// ////// 万一 结束过程2; -------------------------------------------------- -------------------------------------------------- --- 但我也陷入了同样的问题，这个案例只执行了一次，只是data1被读取和处理!!!!!! 你有什么问题，因为在同一块ram上读/写同时???? 虽然读/写发生在单独的端口或阻塞内存...... 以上来自于谷歌翻译 以下为原文 Do you have two distinct case statements inside one process? yes of course What happend if you split the two case statements over two processes (effectively ping-pong between the two processes)? I did it but the data didn't come to the second process!!!! , i fall in wrong synchronization............ Look now i am try the following method :: ------------------------------------------------------------------------------------------------------- process1(clk) begin if clk'event and clk ='1' then case2 sel is when 0 => case1 sell is when 0 => read data1 when others => null; end case1; . . . . ////doing processing on data1//// and store the data on frame buffer ((by port a of dual port block ram)) . when 12 => sel => 0; /////to read the data2,data3,and others data to make processing on it when others => null; end case2; end if; end process1; process2(clk) /////// this process is read continuously eventhough the first process writing//////// begin if rising_edge(clk) then ///////////read the data that stored in frame buffer(( by port b of the same previous dual port block ram)) and show it on VGA port //////////////// end if end process2; ------------------------------------------------------------------------------------------------------- but also i fall in the same problem that this case executed only one and just data1 is read and processing !!!!!! do you thing the problem because on read/write on the same block ram at the same time???? although read/write happened at seperate port or block ram...... |
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同时读取和写入RAM可能是一件棘手的事情，但无论数据发生什么，都不应影响进程的处理方式。
你说第一个进程只执行一次。 你是如何验证的？如何剂量增加（或以其他方式改变价值）？ ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 Reading and writing to RAMs simultaneously can be a tricky business but whatever happens to the data should not affect how the processes are handled. You say that the first process only executes once. How are you verifying this? How do sel and sell increment (or otherwise change value)? ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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你说第一个进程只执行一次。
你是怎么验证这个的？ 通过chipcope，我可以看到只有data1出现（请注意，我只是为了读取数据而创建一个进程，data1，data2，data3和所有其他数据出现在芯片范围内，但是当我将它与处理过程结合起来时，它只读取一个并停止 !!!!）,,, sel和sell如何增加（或以其他方式改变价值）？ 我马上换了...... 当0 => sel时 when1 => sel when2 => sel 并改变销售增量出售 以上来自于谷歌翻译 以下为原文 You say that the first process only executes once. How are you verifying this? by the chipscope i can see just data1 is appear (note that if i make a process just for reading data it data1,data2,data3 and all others appear in chip scope , but when i combine it with the processing process it read just one and stop!!!!) ,,, How do sel and sell increment (or otherwise change value)? I change sel immediately .... when 0 => sel <= 1; when 1 => sel <= 2; when 2 => sel <= 3; and change sell incremently sell<=sell+1 in each step |
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我马上换了......
当0 => sel时 when1 => sel when2 => sel 并改变销售增量出售 因此，我根本不清楚为什么你需要在一个过程中有两个选择和两个案例陈述。 两者都选择每步增加1并且不可能跳跃状态（即从1移动到6，或从7移动到3等）。 顺便说一句，我（个人）不喜欢别人=> null; 编码。 如果案件条件是由于某种原因，其他人，你永远不会离开这种状态，有效地冻结你的机器（非常像你似乎见证的那样）。 我也不清楚合成器如何处理这种类型的编码。 我会将一些默认行为编码为更安全。 如果您发布实际代码，而不是伪代码，那么查明问题可能要容易得多，而不是希望找到一些东西。 我相信您可以通过更简单，经典的FSM设计实现您的目标。 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 I change sel immediately .... when 0 => sel <= 1; when 1 => sel <= 2; when 2 => sel <= 3; and change sell incremently sell<=sell+1 in each step It is not clear to me at all, therefore, why you NEED to have two selects and two case statements in one process. Both selects increment by 1 every step and it isn't possible to jump states (i.e. move from 1 to 6, or from 7 to 3, etc.). Incidentally, I (personally) don't like the when others => null; coding. If the case condition was, for some reason, others, you could never leave that state condition, effectively freezing your machine (very much like what you seem to be witnessing). I am also unclear how the synthesiser treats this type of coding. I would encode some default behaviour to be safer. If you posted your actual code, as is, rather than pseudo-code it may be a lot easier to pinpoint issues rather than fish around hoping to find something. I believe that you can achieve what you want with a much simpler, classic, FSM design. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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