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大家好,
谁能告诉我如何在RTL或xilinx spartan FPGA的约束文件中插入1.56ns延迟缓冲区? 这是为了避免xilinx工具在进行合成后报告的保持时间违规。 问候 马赫什 以上来自于谷歌翻译 以下为原文 Hello Everyone, Can anyone tell me on how to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga? This is to avoid hold time violation reported by xilinx tool after doing synthsis. Regards Mahesh |
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15个回答
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延迟只能添加到FPGA输入端口。
定义了2个约束。 1.IBUF_DELAY_VALUE - 可应用于不直接驱动a的任何输入或双向信号 时钟或IOB(输入输出块)寄存器。 值为0到16。 这些值不直接与时间单位相关,而是与额外的缓冲延迟相关。 数据表中提到了这种缓冲延迟。 例如:NET“top_level_port_name”IBUF_DELAY_VALUE = value; 2.IFD_DELAY_VALUE - 可应用于驱动IOB的任何输入或双向信号(输入 值为0到8.这些值与时间单位不直接相关,而是与额外的缓冲延迟直接相关。 数据表中提到了这种缓冲延迟。 输出块)寄存器。 例如:NET“ 希望这可以帮助你...... top_level_port_name“IFD_DELAY_VALUE = value; 以上来自于谷歌翻译 以下为原文 Delay can be added only to FPGA input ports. There are 2 constraints defined. 1. IBUF_DELAY_VALUE - Can be applied to any input or bi-directional signal that is not directly driving a clock or IOB (Input Output Block) register. Value is 0 to16. These values do not directly correlate to a unit of time but rather additional buffer delay. This buffer delay is mentioned in datasheets. Ex: NET "top_level_port_name" IBUF_DELAY_VALUE = value; 2. IFD_DELAY_VALUE - Can be applied to any input or bi-directional signal which drives an IOB (Input Value is 0 to 8. These values do not directly correlate to a unit of time but rather additional buffer delay. This buffer delay is mentioned in datasheets. Output Block) register. Ex: NET " Hope this helps you... top_level_port_name" IFD_DELAY_VALUE = value; |
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嗨,
感谢您的快速回复。 我实际上意味着如何通过使用xilinx ISE工具在RTL中添加延迟缓冲器来修复1.56ns的保持时间违规? 此外,有没有什么办法可以通过增加约束文件中特定信号(报告保持时间违规)的输出延迟来解决这个保持时间违规问题? 问候 马赫什 以上来自于谷歌翻译 以下为原文 Hi, Thanks for the quick reply. I actually meant how a hold time violation of 1.56ns be fixed by adding delay buffer in RTL using xilinx ISE tool? Also, is there any way we can fix this issue of hold time violation by increasing the output delay of that particular signal (where hold time violation is reported) in constraints file? Regards Mahesh |
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嗨克里希纳,你能不能再详细说明你的答案了。
就像将输出延迟插入的语法一样。 你能帮我举个例子吗?关心马赫什 以上来自于谷歌翻译 以下为原文 Hi Krishna, Can you please eloborate your answer little bit more. Like what is the syntax for inserting delays to outputs. Can you help me with an example? Regards Mahesh |
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据我所知,没有选择为OBUF添加延迟。
我有一个直截了当的问题。 对于FPGA中的触发器,您是否遭到保持违规? 以上来自于谷歌翻译 以下为原文 As i know, there is no option to add delay to OBUF. I have a straight question. For which flip-flop in FPGA, you are getting hold violation? |
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嗨,这是一个D-Flip Flop.RegardsMahesh
以上来自于谷歌翻译 以下为原文 Hi, Its a D-Flip Flop. Regards Mahesh |
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我的意思是说你在哪种情况下遭到违规?
以上来自于谷歌翻译 以下为原文 I mean to say in which scenario you are getting hold violation? |
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maheshpenugonda写道:
大家好, 谁能告诉我如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区? 这是为了避免xilinx工具在进行合成后报告的保持时间违规。 问候 马赫什 这是两个内部触发器之间的保持时间违规,还是连接到输入引脚的寄存器? ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 maheshpenugonda wrote: Is this hold-time violation between two internal flip-flops, or is it on a register connected to an input pin? ----------------------------Yes, I do this for a living. |
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嗨,
这是我得到的确切报告。 松弛(保持路径):-1.379ns(要求 - (时钟路径+时钟到达+不确定性 - 数据路径))源:hsic_data(PAD)目的地:hub_top_inst / u_utmi_hsic / inst_sp6_fpga_hsic_ddr / inst_ddr_data_rx / rx_ddr_inst / f_data_n(FF)目的地时钟: N625下降到0.000ns要求:0.300ns数据路径延迟:2.148ns(逻辑电平= 1)(仅限组件延迟超出约束)时钟路径延迟:3.802ns(逻辑电平= 2)时钟不确定度:0.025ns 频率为240MHz 它是DDR操作的。 问候 马赫什 以上来自于谷歌翻译 以下为原文 Hi, This is the exact report i got. Slack (hold path): -1.379ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: hsic_data (PAD) Destination: hub_top_inst/u_utmi_hsic/inst_sp6_fpga_hsic_ddr/inst_ddr_data_rx/rx_ddr_inst/f_data_n (FF) Destination Clock: N625 falling at 0.000ns Requirement: 0.300ns Data Path Delay: 2.148ns (Levels of Logic = 1)(Component delays alone exceeds constraint) Clock Path Delay: 3.802ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Frequency is 240MHz and it is DDR operated. Regards Mahesh |
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嗨,这是我得到的报告。
松弛(保持路径):-1.379ns(要求 - (时钟路径+时钟到达+不确定性 - 数据路径))源:hsic_data(PAD)目的地:hub_top_inst / u_utmi_hsic / inst_sp6_fpga_hsic_ddr / inst_ddr_data_rx / rx_ddr_inst / f_data_n(FF)目的地时钟: N625下降到0.000ns要求:0.300ns数据路径延迟:2.148ns(逻辑电平= 1)(仅限组件延迟超出约束)时钟路径延迟:3.802ns(逻辑电平= 2)时钟不确定度:PAD之间0.025nsIts 和flop.Clock频率为240MHz。核心在DDR模式下运行。 以上来自于谷歌翻译 以下为原文 Hi, here is the report i got. Slack (hold path): -1.379ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: hsic_data (PAD) Destination: hub_top_inst/u_utmi_hsic/inst_sp6_fpga_hsic_ddr/inst_ddr_data_rx/rx_ddr_inst/f_data_n (FF) Destination Clock: N625 falling at 0.000ns Requirement: 0.300ns Data Path Delay: 2.148ns (Levels of Logic = 1)(Component delays alone exceeds constraint) Clock Path Delay: 3.802ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Its between a PAD and flop. Clock Frequency is 240MHz The core is operated in DDR mode. |
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您的问题是您有一个高频输入路径,并且您没有使用IO中的寄存器。
您表明这是一个DDR接口,因此您的输入板应连接到IDDR2寄存器以正确捕获此数据。 有关详细信息,请参阅UG381。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Your problem is that you have a high frequency input path and you are not using the registers in the IO. You indicated that this is a DDR interface so your input pad should be connected to an IDDR2 register to capture this data correctly. See UG381 for more details. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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嗨,
谢谢你的建议。 然而,我们最初尝试了此选项,发现设置违规并且没有违规保留时间。 如果有另一种最佳方法可以解决这个问题,请告诉我。 问候 马赫什 以上来自于谷歌翻译 以下为原文 Hi, Thanks for the suggestion. we however tried this option initally and found set up violations and no hold time violations. Let me know if there is another best way to do overcome this problem. Regards Mahesh |
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>感谢您的建议。
然而,我们最初尝试此选项并发现设置违规 >并且没有违规时间。 所以你交易了一个糟糕的情况,甚至更糟糕的情况。 >让我知道是否有另一种最佳方法可以解决这个问题。 实现高速IO接口的最佳方法是使用IOB中的专用逻辑。 尝试使用结构中的寄存器捕获480 Mbps流(240 MHz DDR)将不起作用。 请详细描述您的界面和时间要求,也许论坛可以帮助您解决问题。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > Thanks for the suggestion. we however tried this option initally and found set up violations > and no hold time violations. So you traded one bad situation for an even worse situation. > Let me know if there is another best way to do overcome this problem. The best way to implement a high speed IO interface is to use the dedicated logic in the IOB. Attempting to capture a 480 Mbps stream (240 MHz DDR) using a register(s) in the fabric will not work. Please describe your interface and timing requirements in detail and maybe the forum can help you work through the issues. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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嗨,
我想知道是否有人正在研究高速芯片间USB [HSIC]; USB芯片到芯片的互连协议。 有没有IP,测试台,可用的Tets板? 谢谢, 以上来自于谷歌翻译 以下为原文 Hi, I am wondering if anyone is working on High-Speed Inter-Chip USB [HSIC]; a USB chip-to-chip interconnect protocal. Is there any IP, test bench, tets board available? Thanks, |
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@布赖恩,
您应该打开一个新线程,开始讨论一个不相关的主题或问题,例如这个。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 @brian, You should open a new thread to begin a discussion of an unrelated topic or question such as this. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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