一个MCB模块的地址和控制是否可以共享到2个DDR3

不要尝试，我相信它不会起作用。
两个MCB必须在*完美*锁定步骤中操作，并且在UG388中没有提到这样的功能
如果要保存VTT终端电阻，请考虑以下选项：
*为每个DDR3使用单独的点对点地址+控制总线，采用Spartan 6片上终端功能实现源串联终端
*保持走线长度短
*根据迹线的阻抗，选择CALUNED_25，UNTUNED_50或UNTUNED_75或SSTL15固有的（大致）20欧姆。
使用模拟器（HyperLynx或spice）检查SI。
另一种选择是使用配置为32位宽DDR3的软DRAM控制器。
考虑将两个DDR3安装在“蛤壳”配置中，以允许地址+ cotrol总线的串联终止（如上所述）
斯蒂芬Ecob
硅的灵感
悉尼，澳大利亚
www.sioi.com.au
39美元Spartan 6主板配32MB DDR DRAM？
http://www.sioi.com.au/shop/product_info.php/products_id/47



以下为原文

Don't try it, I'm sure it won't work.  The two MCBs would have to operate in *perfect* lock step, and there is no mention of such a capability in UG388
 
If you want to save on VTT termination resistors then consider this option:
* Use separate point to point address+control busses for each DDR3 with source series termination implemented with the Spartan 6 on chip termination feature
* Keep the trace length short
* Select UNTUNED_25, UNTUNED_50, or UNTUNED_75 or the (roughly) 20 ohms intrinsic to SSTL15 according to the impedance of your traces.  Use a simulator (HyperLynx or spice) to check SI.
 
Another alternative would be to use a soft DRAM controller configured for 32 bit wide DDR3.  Consider mounting the two DDR3s in a "clam shell" configuration to allow series termination (as described above) of the address+cotrol bus
 
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$39 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47
 

我们的要求需要一个32位DDR3接口，因此我们计划使用2个MCB模块作为单个32位总线
Xilinx Spartan-6工具支持两个16位控制器，但不支持单个32位控制器。
您正在“规划”的配置在Xilinx文档中特别提及为不受支持。
任何人都可以告诉我们一个MCB模块的地址和控制是否可以共享到2个DDR3，而另一个MCB模块的地址是否可以保持打开状态？
MCB设计不支持此配置。
我理解您对此配置的兴趣，并且可以使用软（非MCB）控制器设计进行此类配置。
在我们的设计中，我们可以节省VTT上拉和开盖的位置。
如果可能，请告诉我们。
UG388“书籍”指南和SP605设计使用地址/控制组信号的并行终止。
然而，在这些论坛中已经描述了几种Spartan-6设计，这些设计使用串联终端或没有外部终端用于地址/控制组信号，完全避免了对VTT电源调节器的需求。
DDR3存储器接口的传输线与其他信号没有区别，因此可以并且可以应用声音信号完整性实践。
使用内部Spartan-6输出驱动器的固有阻抗可能完全适用于点对点连接。
用于模拟的IBIS模型随时可用。
要正确量化信号行为，您需要知道电路板上用于模拟信号的走线长度。
论坛搜索很容易就此主题进行相关讨论。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

our requirement needs a single 32 bit DDR3  interface, so we are planning to use 2 MCB blocks as single 32bit bus
 
Xilinx Spartan-6 tools support two 16bit controllers, but not a single 32bit controller.  The configuration you are 'planning' is specifically mentioned in Xilinx docs as unsupported.
 
Can any one let us know if the address and control from one MCB block can be shared to the 2 DDR3's and the address from the other MCB block can be left open?
 
This configuration is not supported by MCB design.  I understand your interest in this configuration, and such a configuration is possible with a soft (non-MCB) controller design.
 
We can save the place of VTT pullups and decaps as place is constraint in our design. Let us know if this possible.
 
The UG388 'book' guidelines and the SP605 design use parallel termination of the address/control group signals.  However, several Spartan-6 designs have been described in these forums which use either series termination or no external termination for the address/control group signals, entirely avoiding the need for a VTT supply regulator.
 
Transmission lines are no different for DDR3 memory interfaces than for other signals, so sound signal integrity practices can and may be applied. Using the intrinsic impedance of the internal Spartan-6 output driver may be entirely adequate for point-to-point connections.  The IBIS models for simulation are readily available.  To properly quantify the signal behaviour, you will need to know the trace lengths on the circuit board for the signals being simulated.
 
A forums search will easily turn up related discussions of this subject.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
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正如其他人所指出的那样，不，你不能以你提到的方式分享MCB。
但是有一个关于将MCB与用户逻辑结合起来的应用笔记：http：//www.xilinx.com/support/documentation/application_notes/xapp496.pdf。
也许这会有所帮助。



以下为原文

As others have pointed out, no, you can't share MCB's in the way you mention.  But there is an app note on combining MCB's to appear as one to the user logic: http://www.xilinx.com/support/documentation/application_notes/xapp496.pdf.  Perhaps that would help.

谢谢回复。
我浏览了XAPP496并了解到它们可以在MCB之后在用户界面级别内部组合。
但我想知道的是我是否可以将2个独立的16位内存块合二为一。
我已将2个独立的记忆连接到MCB，并且还可以独立延迟匹配。
如果长度匹配的长度不同，这是否有效。
由于我们的设计处于最后阶段，因此对快速响应表示赞赏。
谢谢，
尔法恩



以下为原文

Thanks for the reply.
 
I went through the XAPP496 and understood that they can be combined inside at the user interface level after MCB. But all I want to know is whether I can combine 2 independent 16 bit memory blocks into one. I have connected 2 separate memories to  MCB's and also delay matched independently. Will this work if they are length matched independently with different length.
 
Quick response is appreciated as our design is in a final stage.
 
Thanks,
Erfan

我浏览了XAPP496并了解到它们可以在MCB之后在用户界面级别内部组合。
但我想知道的是我是否可以将2个独立的16位内存块合二为一。
我已将2个独立的记忆连接到MCB，并且还可以独立延迟匹配。
如果长度匹配的长度不同，这是否有效。
这取决于（我们未知）与FPGA设计和电路板设计相关的变量和注意事项。
根据您所披露的内容很少，很难（或不可能）做出任何断言，即您的设计方法将会或不会按预期工作。
第一个简单的答案是：
如果您期望的不超过Spartan-6数据表（DS162）所保证的，那么您就是坚实的基础。
如果您的设计需要通常在DS162中定义或描述的性能保证，那么您可能会将您的设计置于风险之中。
根据设备数据表中无法保证的行为或性能，既不合理也不谨慎。
第二个简单的答案是：
模拟你的设计。
1和0的逻辑仿真，信号完整性和电路板延迟的模拟仿真。
您是否考虑过打开网页，并使用Xilinx代表讨论您的设计细节？
这可能是您的最佳途径，特别是如果您认为可能需要对数据表规格进行特殊解释。
由于我们的设计处于最后阶段，因此对快速响应表示赞赏。
一般而言，在设计经过严格审查，所有主要风险项目均已确定并得到解决之后，“最终阶段”特征将被保留，并且设计的基本性能要求已得到证明并证明是可实现的。
如果没有这个标准，设计和产品（和时间表）可能会有风险，因此“最后阶段”不是一个合理的特征。
如果您不确定设计中存在的风险，最好提请项目经理注意 - 尽快而不是以后。
如果您能找到保证成功的设计路径（即保持在数据表的描述范围内），您将成为项目的英雄。
如果原型电路板不能可靠和有效，那么最终可能会成为项目的弃儿。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

 
I went through the XAPP496 and understood that they can be combined inside at the user interface level after MCB. But all I want to know is whether I can combine 2 independent 16 bit memory blocks into one. I have connected 2 separate memories to  MCB's and also delay matched independently. Will this work if they are length matched independently with different length.
 
This depends on (unknown to us) variables and considerations related to both your FPGA design and the circuit board design.  Based on what little you have disclosed, it is difficult (or impossible) to make any assertions that your design approach either will or will not work as you expect.
 
The first simple answer is:
 

• If you are expecting no more than what the Spartan-6 datasheet (DS162) guarantees, you are on solid ground.
  

• If your design requires performance assurances which are not generally defined or described in DS162, then you are possibly putting your design at risk.  Depending on behaviour or performance which is not guaranteed in the device datasheet is neither reasonable nor prudent.
  

The second simple answer is:
 

• simulate your design.  Logic simulation for the 1s and 0s, analogue simulation for signal integrity and circuit board delays.
  

Have you considered opening a webcase, and discussing very detail of your design with a Xilinx rep?  This may be your best path, especially if you think you might need special interpretation of the datasheet specs.
 
 Quick response is appreciated as our design is in a final stage.
 
Generally speaking, the 'final stage' characterisation is reserved until the design has been rigorously reviewed, all major risk items have been identified and resolved, and the fundamental performance requirements of the design have been demonstrated and proven to be achievable.  Short of this standard, the design and product (and schedule) are potentially at risk, and therefore 'final stage' is not a reasonable characterisation.
 
If you are uncertain about the risk in your design, it is always a good idea to bring this to the attention of the project manager -- sooner rather than later.  If you can find a design path for which success is guaranteed (i.e. stay within the described bounds of the datasheet), you will be the project hero.  If the prototype circuit board can't be made reliable and functional, you might end up being the project outcast.

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.