由缓存和优化引起的DMA问题

我有三个DMA通道从内存缓冲器输出到SPI，DMA设置在定时器中断例程（VGA生成）中发生，我遇到一个问题，当缓冲存储器被主程序中的代码更新时，DMA的输出不会改变。如果我做了第二次改变，DMA然后更新到前一个。即内存正确更新，但DMA直到另一个内存访问发生时才看到变化。如果从程序的不同部分进行内存读取，DMA输出也会自行校正。我试着把一个读放到更新例程中，但是缓存太聪明了，不能被删除，DMA保持不正确。看来内存更新被困在缓存中，或者优化器正在保持寄存器的变化。我认为这是缓存，因为我已经尝试用AyAtAtditTyx编译内存写代码（（优化（-O0））），并且更改是多字节的。有没有办法确保物理内存写回在我的更新缓冲程序结束时被强制。我已经看过了关于VILO V2.01B文档中PLIB预取缓存库的章节，但是看不到我需要做什么。谢谢所有的建议。



      以下为原文

    I've got three DMA channels outputting from a buffers in memory to SPI with the DMA setup happening inside a timer interrupt routine (VGA generation)

I'm having a problem that when the buffer memory is updated by code in the main program the output from the DMA doesn't change. If I then do a second change the DMA then updates to the previous one. i.e. the memory is updating properly but the DMA isn't seeing the change until another memory access happens.

The DMA output also corrects itself if I do a memory read from within a different part of the program. I've tried putting a read into the update routine but the caching is too clever to fall for that and the DMA stays incorrect.

It appears that the memory update is stuck in cache and/or the optimiser is keeping the change in registers. I think it is the caching because I have tried compiling the memory write code with __attribute__((optimize("-O0"))) and the changes are for many bytes.

Is there a way to ensure that physical memory write-back is forced at the end of my update buffer routine. I've looked at the chapter on the plib pre-fetch cache library in the HARMony v2.01b documentation but can't see what I need to do.

Thanks for all suggestions.