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亲爱的四人，
IM试图将DMA滤波器结果从保持寄存器直接传送到8位控制寄存器。我一直在使用DMA向导来生成配置DMA所需的代码。当编译IM出错时，我不知道该怎么办。 下面是向导正在生产的内容。 /*变量声明用于FieltDoEnEdMaLoL*/*将这些变量声明移到函数*/Unt8 FieltDoEnEdMaLoLo.Chanin的顶部；UtiN FiTr.DoEnEddMaLoLoTd（1）；/*DMA配置为FieltOnEdEdMaLoL*/y*定义FieldDoEnEdMaLoLyByTeSePySype 1定义定义FieldDoEnEdMaLoLoRealEvestBug一个突发1定义了FieldDoEnEdMaLoLo.SrcBASE（CyDeVelEnguriBaseBasic）定义了FieldDoEndMaLoLo.dSTyBASE（CyDeVelEnguriBaseBASE）文件。Hi16（FiTr.DoEnEddMaLo.dStdBase）；FieldDoEndMaLoLoToD（0）＝CydMatDLaTestAd（）；CytMatDeStDead配置（FieltDoEndodMaLoLoTd〔0〕，1，DMAIN SimuldIdTd，0）；CytMatDeStAdt地址（FieltDoEnEdMaxLooTd [0），Lo16（（UTI32）Fielt1 1HOLDAY-PTR），Lo16（（UTIT32）CrtLl ReGig FieltLoCuxFieldPtR）；CyDmaChSetInitialTd（FieltDoEndodMaLoLuang-Chanin，FieltDoEnEdEdMaLoxTd〔0〕）；CyDmaChEnable（FieltDoEndodMaLoLohanChank，1）； 错误消息是 PRJ.M0120：'crtLyReqFieltLoLySycScLLCrgRiguxPultReultReg未声明（在这个函数中首次使用） 我所做的其他DMA还没有像VAR这样未被声明的问题。 *定义cTrl ReGyStGyCurrTyLoLoCuffel.PtR（（Req8*）cTrLGReGythSuxCurrntLoSycCyrcTrLGRiguxCuxFieldReg 创建者2.2.0.93和运行的CY8CKIT-050与PSOC5LP部分。 谢谢你的帮助。 马特 以上来自于百度翻译 以下为原文 Dear Fourm, Im attempting to transfer with the dma filter results from the holding register directly to a 8 bit control register. I have been using the dma wizard to produce the needed code for configuring the dma. When compiling Im getting a error Im not sure what to do with. Here is what the wizard is producing. /* Variable declarations for FILT_DONE_DMA_LO */ /* Move these variable declarations to the top of the function */ uint8 FILT_DONE_DMA_LO_Chan; uint8 FILT_DONE_DMA_LO_TD[1]; /* DMA Configuration for FILT_DONE_DMA_LO */ #define FILT_DONE_DMA_LO_BYTES_PER_BURST 1 #define FILT_DONE_DMA_LO_REQUEST_PER_BURST 1 #define FILT_DONE_DMA_LO_SRC_BASE (CYDEV_PERIPH_BASE) #define FILT_DONE_DMA_LO_DST_BASE (CYDEV_PERIPH_BASE) FILT_DONE_DMA_LO_Chan = FILT_DONE_DMA_LO_DmaInitialize( FILT_DONE_DMA_LO_BYTES_PER_BURST, FILT_DONE_DMA_LO_REQUEST_PER_BURST, HI16(FILT_DONE_DMA_LO_SRC_BASE), HI16(FILT_DONE_DMA_LO_DST_BASE)); FILT_DONE_DMA_LO_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration( FILT_DONE_DMA_LO_TD[0], 1, DMA_INVALID_TD, 0); CyDmaTdSetAddress( FILT_DONE_DMA_LO_TD[0], LO16((uint32)Filter_1_HOLDA_PTR), LO16((uint32)CTRL_REG_FILT_LO_Control_PTR)); CyDmaChSetInitialTd(FILT_DONE_DMA_LO_Chan, FILT_DONE_DMA_LO_TD[0]); CyDmaChEnable(FILT_DONE_DMA_LO_Chan, 1); The error message is prj.M0120:'CTRL_REG_FILT_LO_Sync_ctrl_reg__CONTROL_REG' undeclared (first use in this function) The other dmas I have done I have not had a issue like this where the var is undeclared. #define CTRL_REG_SET_CURRENT_LO_Control_PTR ( (reg8 *) CTRL_REG_SET_CURRENT_LO_Sync_ctrl_reg__CONTROL_REG ) Creator 2.2.0.293 and running cy8ckit-050 with a psoc5lp part. Thanks for the help. Matt 
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9个回答
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当你处于测试阶段时，可能是你还没有连接任何硬件到控制寄存器。因此，优化器可能已经删除它，从而导致上述错误。
鲍勃 以上来自于百度翻译 以下为原文 When you are in the stage of testing it might be that you do not have connected any hardware to the control-register yet. Thus the optimizer might have removed it which results in the above error. Bob |
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鲍勃，
谢谢您。就是这样。我有一个控制比较器连接到一个数字比较器，但没有连接到一个IO引脚，所以是的，它是优化了。再次感谢您的帮助！！！！ 马特 以上来自于百度翻译 以下为原文 Bob, Thank you. That was it. I had the control regs connected to a digital comparator, but that was not connected to a io pin so yes it was being optimized out. Again Thank you for your help!!! Matt |
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我现在有一个类似的问题，同时使用PSoC SESESEI并行FIFO输入。IT职位：
M0120：“FIFONIN 1AASCYCTCLFECTRIGEGRIGEXPROTER REG”未声明。 我在.h文件和.c文件中找到了它的声明，其结果如下： h：y定义FIFONIN 1X控件Reg（*（ReG8*）FIFONIN 1AASCTCTLKORKEGRIGEX CONTROL CORDER REG）。C：FIFONIN 1ICONTRORIGRYG＝FIFONIN 1EN；再加上调用控制RG的其他2个位置。 我使用PSoC 5LP DEV工具包050A，当我在PSoC 5开发工具包中运行它并运行良好。我正在测试它，就像鲍勃回答的那样，但是我不知道修复是什么，或者更确切地说，是什么“GrimyFlash”解决了RuPrTM的问题。我可以告诉大家，所有的连接都是在正确的位置上进行的，没有任何东西是悬空的。这可能是一个问题的交叉兼容性的FIFO与PSoC 5LP，因为它是为PSoC 3开发？我已经附上我的主要文件，以及我的设计迄今为止的屏幕截图。谢谢大家给我的任何帮助！ 以上来自于百度翻译 以下为原文 I am currently having a similar issue while using the PSoC Sensei Parallel FIFO Input. It posts: M0120: 'FIFOIn_1_AsyncCtl_ControlReg__CONTROL_REG' undeclared. I found the declaration in the .h file and .c file it refers to with the following outcome: .h: #define FIFOIn_1_CONTROL_REG (* (reg8 *) FIFOIn_1_AsyncCtl_ControlReg__CONTROL_REG) .c: FIFOIn_1_CONTROL_REG |= FIFOIn_1_EN; plus 2 other locations where the control reg is called. I am using the PSOC 5LP dev kit 050A, when I ran this in the PSOC 5 dev kit it compiled and ran fine. I am currently testing it, as Bobs reply had elluded to, but I am not sure what the fix was, or more precisely what the "flash of genious" was that solved rupertm's problem. As best I can tell I have all connections made to the proper locations and nothing is left hanging. Is this possibly an issue with cross compatability of the FIFO with PSOC 5LP, since it was developed for the PSOC 3? I've attached my main file as well as a screen shot of my design thus far. Thank you ahead of time for any help anybody can give me! |
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上传丢失，使用IE而不是Chrome
鲍勃 以上来自于百度翻译 以下为原文 Uploads are missing, use ie and not chrome Bob |
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对不起，他们现在应该附上，谢谢你的帮助。
PSO55LPTestDMA.ZIP 44.6 K 以上来自于百度翻译 以下为原文 Sorry, they should be attached now, thank you for your help.
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我解决了这个问题，我只是想发布我的解决方案，以防这种情况发生在任何人身上，并验证我的解决方案是一个免费的bug（它可能不是，但它的工作原理）。我必须修改FIFOIN Verilog文件。它似乎正在尝试验证PSoC 5ES1或PSoC3芯片是否被使用，如果不是，它没有同步寄存器（或者这种性质的东西）。在“FIFONIVIV1O.V.0”的第145行，用“IF（PSoC3OS2，PSO55ES1）”检查AsYCCTL。我简单地改变了这一行来读取“如果（PSoC3OS2，pSOC5Se1（1）”），这样它总是正确的，并且总是同步控制寄存器。除了一些持久的时钟警告之外，该代码现在按预期的方式编译。
如果有人暗示我为什么会得到下面的警告，我会很感激反馈（可能属于不同的论坛帖子，我希望尽可能完整地完成这个帖子）： 警告-1366：在从时钟（CyBuxCLK）到时钟（CyBuxCLK）的路径中发现设置时间违反。 谢谢您！ 以上来自于百度翻译 以下为原文 I solved this issue, I just wanted to post my solution in case this occurs to anyone else and to verify that my solution is one free of bugs (which it probably isn't but it works). I had to modify the FIFOIn verilog file. It seems that what it was doing was trying to verify that either PSOC 5ES1 or PSOC3 chips were being used, if not it was not syncing the register (or something of this nature). On line 145 of "FIFOIn_v1_0.v" the AsyncCtl is checked with "if(PSOC3_ES2 || PSOC5_ES1)". I simply changed this line to read "if(PSOC3_ES2 || PSOC5_ES1 || 1)" so that it is always true and always syncs the control register. The code compiles now as works as expected, aside from some persistent clock warnings. If anyone has any hints as to why I'm getting the following warnings I'd appreciate the feedback (probably belongs in a different forum post but I wanted to make this post as complete as possible): Warning-1366: Setup time violation found in a path from clock (CyBUS_CLK) to clock (CyBUS_CLK). Thank You! |
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对于你的问题：简短的回答：你有一个计时问题。
长的回答：可能是你的总线时钟速度对于你的设置来说太高了，或者超过了组件的TimIf/频率限制。“设置时间”指的是一个组件需要某个信号停留在其逻辑级别的时间，以便它能够正确地处理它。（例如，当你有一个DFF时，它要求D输入的电平在时钟线变高之前（甚至在之后）短时间内是恒定的——如果它没有得到未确定的结果）。 您可以打开静态时序报告，并查看此错误发生的位置。如果你知道所涉及的组件和信号，你可以试着弄清楚情况。 以上来自于百度翻译 以下为原文 To your question: short answer: you have a timing problem. Long answer: It might be that your bus clock speed is too high for your setup, or that you exceed the timinf / frequency limits of a component. "setup time" refers to the time a component requires a certain signal to stay at its logical level so it can properly handle it. (E.g. when you have a DFF, it requires the level on the D input to be constant for a short period before (and maybe even after) the clock line goes high - if it doesn't you get undetermined results). You can open the static timing report, and look where this error happens. If you know the components and the signals involved, you can try to clear the situation. |
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谢谢你的答复，你肯定是正确的，这是一个时间问题，但如何解决它是一个很好的问题。我需要把总线时钟降到43兆赫（正如静态时序分析），但这似乎是不必要的，因为项目中的其他一切都以这样的速度运行得很好，而且我真的需要额外的时钟周期来处理CPU进程并保持在我的数据收集之前。我想让时钟通过Verilog中的除法器，从而修改控制寄存器本身看到的时钟，但我不太熟练用Verilog来实现这一点。是否有任何教程或参考文献能解释我正在努力完成的这一方面？我希望一切都清楚，如果不是，请让我知道我应该清理什么。谢谢您。
以上来自于百度翻译 以下为原文 Thank you for the response, you are certainly correct that it is a timing issue, but how to solve it is a good question. I would need to take the bus clock down to 43 MHz (as says the static timing analysis), but this seems unnecessary since everything else in the project runs fine at that speed, and I really need the extra clock cycles to handle CPU processes and stay ahead of my data gathering. I'd like to put the clock through a divider within the verilog, thus modifying the clock that the control register itself sees, but I'm not proficient enough with verilog to accomplish this. Is there any tutorials or references anybody has that would explain this aspect of what I'm trying to accomplish? I hope everything is clear, if not please let me know what I should clear up. Thank you. |
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如果你能识别受影响的组件，你可以用较低的时钟给它，并且为其余的使用最高可能的时钟（尤其是核心，如果你需要最大CPU速度）。您不必在Verilog中执行此操作，只需在受影响的组件上安装外部时钟即可。
以上来自于百度翻译 以下为原文 If you can identify the affected component, you can feed it with a lower clock, and use the highest possible one for the rest (esp. the core, if you need maximum CPU speed). You don't need to do this necessarily within verilog, you just need an external clock on the affected component. |
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