请问怎么同时使用ADC和DAC？

你好
我认为它们不能同时使用，因为SPI总线（MOSI，MISO，SCK）信号是共享的。
有关详细信息，请参阅Spartan-3E FPGA入门工具包用户指南的第9章和第10章：http：//www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf。
因此，您必须使用某种机制，例如交替启用和禁用这些设备，以及使用内存来存储从ADC捕获的样本。
这是我的想法。
因为你使用过ADC，我对它的操作有疑问：当我加载Amp时。
通过其8位定标设置并将CS / LD引脚置为1，该模式信号捕获期间该引脚必须为1，或者在将比例设置加载到Amp后将其返回到零。
???
（在我的项目中，我需要以恒定的增益记录整个信号）。
OMS



以下为原文

Hello
 
i think they can not be used as the same time because the SPI bus (MOSI , MISO , SCK) signals are shared .
 
for more details see chapter 9 and 10 of Spartan-3E FPGA Starter Kit Board User Guide : http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf .
 so you must use a certain mechanism like enabling and desabling these devices alternately and to use a memory to store the sample that captured from ADC .
This is my idea about that.
because you was used the ADC , I have a question on its operation : when i load the Amp. with its 8 bit scaling setting and assert the CS/LD pin to 1 , Is this pin must 1 during analog signal capturing or to return it to zero after scale setting has been loaded to Amp. ???
( in my project i need to record the whole signal in a constant gain ).
 
oms

你也可以给我发一个VHDL代码，用于通过Amp从头J7捕获模拟信号。
和ADC，
我也有一个斯巴达3E入门套件。
谢谢
OMS



以下为原文

also can you send me a VHDL code for capturing an analog signal  from header J7 via the Amp. and ADC ,
i have a spartan 3E starter kit too.
 
Thanks
oms

试试这个核心......
我不久前开发了它....
还有一个ADC / AMP测试平台
adc.rar 5 KB



以下为原文

Try this core...
 
I developed it some times ago....
 
there is also a testbench for ADC/AMP
            adc.rar ‏5 KB

亲爱的alexgiul，
非常感谢玩具回答我。
。
。
我读了你的代码，我有以下问题： -
1.此代码是否在spartan3E stater kit上实现？
2.在ADC / AMP.vhd代码的以下部分： -
if index1 = 13 thenADC1（index1）elseADC1（index1）end if; index1：= index1 -1; sample
为什么你采用每个样本的第一位捕获（m***）的补码（标记为粗体字），这个IF的功能是什么？
3. SCK不得超过10 MHz来设置AMP增益（参见http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf的第10章），我认为它在代码中更高。
4. state_type中以下首字母缩写词（HI，LO）的长名称是什么？
你可以将以下翻译成英文，请： -  
* inizio a campionare。 
* LO_UMMY中的ci passo una solavoltadobodichèlaassegno。 
* rappresentazione in complemento a 2。
最后，我非常感谢你。
。
。
谢谢。
OMS



以下为原文

Dear alexgiul,
Thank toy very much for answering me . . .
 
I was read your code and i have the following questions :-
 
1. Is this code implemented on spartan3E stater kit befor ?
 
2. In the follwoing part of ADC/AMP.vhd code :-
if index1 = 13 then
      ADC1(index1)  <= not SPI_MISO;
     else
      ADC1(index1)  <= SPI_MISO;
     end if;     
     index1 := index1 -1;
     sample <='1';
Why you take the complement of the first bit captured (m***) of each sample (marked as bold font), what is the function of this IF ?
 
3. The SCK must not exceed the 10 MHz for setting the AMP gain (see chapter 10 of  http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf) , and i think it higher in your code .
 
4.What is the long name of the following acronyms ( HI , LO ) in state_type ?
 
5.Can you translate the following to english, please :-
  * inizio a campionare .
  * ci passo una sola volta dopodichè la assegno in LO_DUMMY.
  * rappresentazione in complemento a 2.
 
Finally , I thank you very much . . .
Thanks.
 
oms

你好，
感谢您的回复。
当我试图使ADC工作时，我使用了Alexgiul的ADC_AMP代码。
感谢Alexgiul，我可以让ADC工作。
但是代码确实存在一些错误。
我改变了，我纠正了错误。
我附上了它。
Miraç
ADC＆amp; AMP.txt 6 KB



以下为原文

Hello,
Thanks for your reply.
When I was trying to make ADC work I used Alexgiul's ADC_AMP code. Thanks to Alexgiul, I could make ADC work. But it is true that code have some mistakes. I have changed and I corrected the mistakes. I attached it.
Miraç
 
 
 
            ADC&.txt ‏6 KB

你好 。
。
。
谢谢你的回答
20502320感谢您的工作，但我仍然对您的代码有疑问：
1.您是否同意我必须在启动时的信号声明中给出信号（状态）初始值（：= IDLE）。
2.为什么在启动时启用SPI_serial闪存（SPI_SS_B
3.带有整数计数器的代码比二进制代码更具可读性。
4.为什么在（LO_AD状态）中捕获低部分os（SCK）的（SPI_MISO）位。
请你回答我的问题。
谢谢
OMS



以下为原文

Hello . . .
 
Thanks for your answering
 
20502320 thanks for your work , But i still have questions about your code :
 
1. Do you agree me that signal ( state ) must be given an initial value (:= IDLE) in signal declarations at starting .
 
2. Why you enabled the the SPI_serial flash at starting ( SPI_SS_B <= '0') . it's disable value = 1 .
 
3. the code with integer counters is more readable that with binary one .
 
4. Why you captured the (SPI_MISO) bits at low part os (SCK) in the (LO_AD state ) .???
 
can you answer my questions , please .
Thanks
oms

你好
我不给州的初始价值，但我想这并不重要。
但我认为给出初值是件好事。
我在这个论坛中看到这个在Spartan 3E串行闪存的使能位数据表中是高电平有效。
所以da sheet错了。
你应该给它0。
当SCK = 0时，最好捕获MISO。因为ADC将MISO总线上的值置于SCK = 1但是它有一些建立时间延迟。
因此，当你在SCK = 0时捕获MISO时，你会后悔这个延迟并且你的数据是真的。



以下为原文

Hello
I do not give initial value to states but I guess it is not important.  But I think it is good to give initial value.
I read this in this forum that in data sheet of Spartan 3E Serial Flash's enable bit is active high. So da sheet is wrong. You should give 0 to it.
It is better to capture MISO when SCK = 0. because ADC puts the values on MISO bus at SCK = 1. But it has some settling time delays. So when you capture MISO at SCK = 0 you regret this delay and your data is true. 
 

我想在vhdl和verilog中分别为adc和dac代码



以下为原文

i want seperate code for adc and dac both in vhdl and verilog

大家好
我一直在使用亚历克斯的ADC代码。
然而当下载到目标（斯巴达3E评估孩子来自XC3S500）时，ADC输出始终保持在高位可以有人解释什么事情？
--------------------------------------------------
--------------------------------------------------
-------------------------计算机先生似乎知道。
compueter先生可以解释如何编程ADC并在alex中发现程序中的错误
谢谢



以下为原文

Hi all
 
I have been working with the code of the ADC of alex.
however when downloading to the target (spartan 3E evaluation kid from XC3S500) ADC outputs always remain in high Could someone explain what's the matter?  -----------------------------------------------------------------------------------------------------------------------------
Mr Computer seems to know.
Could Mr compueter explain how to program the ADC and found errors in the program by alex
thanks

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以下为原文

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