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该链包含XC3S2000,XCF08P和莱迪思CPLD。
该电路的先前版本运行良好:它有一个XC3S1500代替'2000,而这个链中的第二个XCF08P连接到不在这个链中的其他Spartan-3设备。 在未编程的电路板上,Impact 9.1和Lattice工具都可以看到JTAG链就好了,我可以选择是否对Lattice部分进行编程。 接下来,我使用XC3S2000的配置对XCF08P进行编程。 在电源循环以从闪存配置FPGA之后,两个JTAG工具都无法看到JTAG链。 “Initialize Chain”产生通用的带链错误问题,同时加载匹配的项目文件并尝试对flash进行编程会产生不匹配的ID错误,该错误显示了与未插入的链相同的大多数1s ID。 我们已经尝试在上电前强制INIT_B到复位/ OE线低:结果是链现在可见,Impact可以再次编程XCF08P。 编程以闪存编程后和闪存到FPGA配置期间出现的错误结束,这很有意义,因为我们正在扰乱它们之间的接口。在另一个电源循环之后没有强制INIT_B,符号 来自FPGA逻辑的生命表明它实际上是正确编程的。 通过阻止这样的上电配置来防止锁定强烈暗示(或者可能证明)它是FPGA的实际配置,或者至少是配置过程,使FPGA或XCF08P处于打破JTAG的状态 链。 上电配置过程(或实际的FPGA配置内容)如何导致其中任何一个部分破坏其JTAG链? 这是一个已知的错误或设置问题吗? 旧工作电路与新工作电路之间的其他变化:1。 FPGA上的HTSWP_EN现在接低电平而不是高电平。 (将其绑定为高或N / C会导致甚至未编程的电路板打破其JTAG链。???)2。 不同的电源设置可能导致1.8V电源稍后上升。 如果这会扰乱上电复位并因此干扰配置,那么FPGAG似乎不可能像现在那样活跃起来。 如果这是问题,将INIT_B / Reset保持为低电平,直到上电一段时间后才会导致配置使链条正常工作,对吗? 以上来自于谷歌翻译 以下为原文 The chain contains an XC3S2000, an XCF08P, and a Lattice CPLD. A previous version of this circuit worked fine: It had an XC3S1500 in place of the '2000, and a second XCF08P in this chain connected to other Spartan-3 devices not in this chain. On an unprogrammed board, both Impact 9.1 and the Lattice tool can see the JTAG chain just fine, and I can choose to program the Lattice part or not. Next, I program the XCF08P with the configuration for the XC3S2000. After power-cycling to configure the FPGA from the flash, neither of the JTAG tools can see the JTAG chain. "Initialize Chain" produces the generic problem-with-chain error, while loading the matching project file with and trying to program the flash give the non-matching ID error, which shows the same mostly-1s ID that an unplugged chain would give. We've tried forcing the INIT_B-to-Reset/OE wire low before power-up: Result is that the chain is now visible and Impact can program the XCF08P again. The programming ends in an error that seems to occur post-flash-programming and during flash-to-FPGA configuration, which rather makes sense as we're disturbing the interface between them. After another power-cycle without forcing INIT_B, signs-of-life from the FPGA logic suggest that it was in fact programmed correctly. Preventing the lockup by preventing power-up config like this strongly suggests (or perhaps proves) that it's the actual configuration of the FPGA, or at least the process of configuration, that leaves either the FPGA or the XCF08P in a state of breaking the JTAG chain. How can the process of power-up configuration (or the actual FPGA configuration content) cause either part to break its JTAG chain? Is this a known bug or setting problem? Other changes between the old working circuit and the new: 1. HTSWP_EN on the FPGA is now tied low instead of high. (Tying it high or N/C causes even an unprogrammed board to break its JTAG chain. ???) 2. Different power supply setup which possibly causes 1.8V supply to rise later. If this was disturbing the power-on reset and thus the config, it would seem unlikely that the FPGAG comes alive as it does now. If this was the problem, holding INIT_B/Reset low until some time after power-up should cause proger configuration which leaves the chain working, right? |
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编辑原始帖子,因为在上电期间强制INIT_B到复位/ OE为低电阻以防止Flash配置使JTAG链暂时可用且Flash可重新编程,因此它确实是FPGA配置的内容或(在此过程中出现问题)
使链条断裂的配置。 如上所述 - 我们正在从FPGA中看到生命迹象,因此无论真正发生什么,这样的配置似乎都有效。 FPGA如何配置为中断JTAG? 以上来自于谷歌翻译 以下为原文 Edited original post, because forcing INIT_B-to-Reset/OE low during power-up to prevent configuration from the Flash makes JTAG chain temporarily available and Flash reprogrammable, so it really is the content of the FPGA configuration or (a problem during) the act of configuration that cuases the chain to break. See above - we are seeing signs of life from the FPGA, so no matter what is really going on, the configuration as such seems to work. How can the FPGA be configured to interrupt JTAG? |
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