LIS3DH功耗太高

您是否排除了输入电容器和电路板上的泄漏？如果焊剂残留在电路板上，这可能会导致电路板泄漏，这种情况与此类似。
 
 
您是否在断电模式下测量电流？如果断电电流在规格范围内，则可以排除电容器或电路板泄漏。
 
我希望这不是一个愚蠢的问题，但你的测量电流是否排除了I2C上拉电阻所消耗的电流？这不是指定电流的一部分。



以下为原文





Have you ruled out leakage on the input capacitors, and through the board?  If soldering flux remains on the board, this can cause board leakage plausibly similar to this magnitude.


Have you measured current at power-down mode?  If the power-down current is within spec, you can exclude capacitor or board leakage as the cause.

I hope this is not a silly question, but did your measured current exclude the current drawn by the I2C pullup resistors?  This would not be part of the specified current.

谢谢你的建议。我测量了所有点，我发现没有泄漏。我也相信它不是上拉电阻（虽然我不知道它们的电流被排除在规范之外）。我会尝试使用更高价值的电阻，如果它是I2C，消耗将会下降，对吧？



以下为原文





Thanks for your suggestions. I measured all points and I see no leakage. I also believe it is not the pull-up resistors (although I was not aware their current was excluded from the spec). I will try with higher value of resistors, if it is the I2C the consumtion will go down, right?

I2C电阻是外部的。 I2C器件使用的集电极开路下拉电阻不会将器件的电流增加到Vdd本身，但如果您测量电路板的整个电流，包括I2C上拉电阻（或通过LIS3DH的接地电流），您将看到一些额外的电流。请注意，I2C主机也会从外部下拉电流，但电阻可能与从机一起定位，您可能已将电流表定位为读取该电流。然而，这是不寻常的，通常你是由主人放置电阻器，但这可能只是我。
 
 
如果它们在3.3v系统上是2.2k上拉，并且每个花费5％的时间用于拉低，那么通过它们的平均电流将是150uA。
 
当没有通信时，I2C总线永远不会被拉低。像LIS3DH这样的奴隶从不发起转移。因此，如果您使用主器件配置器件，将其置于连续转换低功耗模式，并停止轮询寄存器，则不会有I2C电流，LIS3DH将继续以连续模式构建采样，即使寄存器永远不会回读，所以你有测量的工作电流。



以下为原文





The I2C resistors are external.  The open-collector pulldowns that I2C devices use will not increase the device's current into Vdd itself, but if you measure the entire current for the board including the I2C pullup resistors (or the ground current through the LIS3DH), you will see some additional current.  Note that the current will also be pulled down externally by the I2C master, but the resistors may be located with the slave and you might have positioned the current meter to read that.  However, this is unusual, usually you place the resistors by the master, but that may just be me.


If they're 2.2k pullups on a 3.3v system, and each spends 5% of the time pulled down, that would be 150uA of average current through them.

When there is no communication, the I2C bus is never pulled down.  Slaves such as the LIS3DH never initiate a transfer.  So if you use the master to configure the device, put it in continuous conversion low-power mode, and stop polling the registers, there will be no I2C current yet the LIS3DH will continue to construct samples in continuous mode even if the registers are never read back, so you have operating current to measure.

你有没有找到为什么你有这么高的消费？
 
 我有或多或少相同的问题 - 更详细地检查它：
 
 在3.4V它消耗c.a. 145μA和2V消耗c.a.断电时45μA所有这些
 模式。
 
 当我发现时，电流由Vdd_IO绘制：
 
 当我断开芯片Vdd的电源时，Vdd_IO＆amp; SC（通过跳线）切断I2C线，我的整个电路板符合规格（5μA）。因此PCB很好。
 
 如果我只连接Vdd，电路仍然在规格范围内。但如果仅连接Vdd_IO或与Vdd和SC一起连接，则上述消耗量由万用表（Agilent 34411A）测量。
 
 数据提议建议仅提供Vdd_IO作为保持总线未被阻塞但断开测量引擎的选项。
 
 当提供所有电源时，我可以读取CTRL_REG1默认值0x07并成功将其设置为0x00
 
 SC应该保持低水平吗？数据表只表明I2C需要很高。
 
 我可以在4-5板上重现这一点。 ST有什么评论吗？ .....



以下为原文





Have you found why you have that high consumption?

I have more or less the same problem - examined it in a bit more detail:

At 3.4V it consumes c.a. 145µA and at 2V it consumes c.a. 45µA all this in power down
mode.

The current is drawn by Vdd_IO as I find:

When I disconnect the power to the chip Vdd, Vdd_IO & SC  (by jumper) and cut the I2C lines my whole board goes within specs (5µA). Hence the PCB is fine.

If I connect only Vdd the circuit is still within specs. But if only Vdd_IO is connected or together with Vdd and SC then the above mentioned consumption is measured by multimeter (Agilent 34411A).

The datasheed proposes supplying only Vdd_IO as an option to keep the bus not blocked but disconnect the measurement engine.

When all power is supplied I can read the CTRL_REG1 default value of 0x07 and successfully set it to 0x00

Should the SC be kept low? The datasheet only says that it needs to be high for I2C.

I can reproduce this on 4-5 boards. Does ST have any comment, please? .....

你好，
 
 我遇到了同样的问题：I2C配置为138μA@ 3.3V。
 尝试将SDO / SA0（引脚7）置于3.3V而不是GND，功耗将降至0.6μA。
 我认为这个引脚有内部上拉电阻。
 在此操作之后，I2C的地址不同，然后更改固件。



以下为原文





Hello,

I had the same problem: 138 µA @3.3V in I2C configuration.
Try to put the SDO/SA0 (pin 7) at 3,3V instead of GND and the power comsuption will go down at 0.6 µA.
I think there is an internal pull-up on this pin.
After this operation the address of I2C is different then change your firmware.

你好，
 
 我在定制设计中遇到了与LIS3DH功耗相同的问题。我想知道将Pin7连接到VCC的解决方案是否适合所有遇到此问题的人。
 我很感激你的帮助，因为ST没有人解决这个问题。
 先谢谢你。干杯。



以下为原文





Hello,

I'm facing the same problem with the LIS3DH power consumption in a custom design. I would like to know if the solution to attach the Pin7 to VCC is working for everybody with this problem.
I would appreciate your help with this as nobody from ST is resolving me this question.
Thank you in advance. Cheers.

我们与LIS3DH有同样的问题。如果ST支持确实知道有关SA0内部上拉的问题，为什么他们不推广勘误表或数据表修订版?????



以下为原文







We have the same issue with LIS3DH. If ST support does know this problem regarding SA0 internal pull up, why they don't promote a errata or datasheet revision?????

我已经尝试将SA0连接到Vcc，但是在100R分流器（-3.6mV）上得到负电压。使用1K分流器，我得到-36mV。怎么会这样呢？
 
 
我在这里先向您的帮助表示感谢。



以下为原文





I've tried connecting SA0 to Vcc, but I get a negative voltage over the 100R shunt (-3.6mV). With a 1K shunt, I get -36mV. How could this be the case?


Thanks for the help in advance.

我要回答我自己的问题。答案不是。如果该引脚保持断开状态，则“上拉”不够强，并在某些条件下振荡。



以下为原文





I am going to answer my own question. The answer is not. If this pin is left disconnected the ''pull-up'' is not strong enough and oscillates under certain conditions.

目前我所测试的也是电流大概160ua一直没办法解决，楼主还尝试过什么方法嘛？