Spartan 3A配置无法复位

确保使用小于1K欧姆的电阻下拉模式引脚
克服内部的“弱”上拉。
在某些情况下，电源排序可能会妨碍正常启动。
您
可以通过暂时将PROG_B引脚接地来测试这是否是您的问题
看看设备是否配置。
实际上没有什么东西可以阻止配置启动和
你已经知道你的电源是O.K.
如果你可以使用该部分
JTAG模式。
所以你真的是模式引脚，可能是INIT和
PROG_B，应该都拉高。
问候，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

Make sure that your mode pins are pulled down with a resistor less than 1K ohms
to overcome the internal "weak" pullups.
 
There are some cases where power sequencing can prevent proper start-up.  You
can test if this is your problem by momentarily grounding the PROG_B pin and
see if the device configures.
 
There really aren't many things that can prevent configuration from starting and
you already know that your power supplies are O.K. if you can use the part in
JTAG mode.  So really you're down to the mode pins and possibly INIT and
PROG_B, which should both be pulled high.
 
Regards,
Gabor
-- GaborView solution in original post

确保使用小于1K欧姆的电阻下拉模式引脚
克服内部的“弱”上拉。
在某些情况下，电源排序可能会妨碍正常启动。
您
可以通过暂时将PROG_B引脚接地来测试这是否是您的问题
看看设备是否配置。
实际上没有什么东西可以阻止配置启动和
你已经知道你的电源是O.K.
如果你可以使用该部分
JTAG模式。
所以你真的是模式引脚，可能是INIT和
PROG_B，应该都拉高。
问候，
的Gabor
-  Gabor



以下为原文

Make sure that your mode pins are pulled down with a resistor less than 1K ohms
to overcome the internal "weak" pullups.
 
There are some cases where power sequencing can prevent proper start-up.  You
can test if this is your problem by momentarily grounding the PROG_B pin and
see if the device configures.
 
There really aren't many things that can prevent configuration from starting and
you already know that your power supplies are O.K. if you can use the part in
JTAG mode.  So really you're down to the mode pins and possibly INIT and
PROG_B, which should both be pulled high.
 
Regards,
Gabor
-- Gabor

另一个问题。
您是否正在使用SPI直接编程
UG332？
或者您是否通过Spartan 3A JTAG使用间接SPI编程？
如果你使用间接模式，那么你可以相当确定你之间的连接
FPGA和闪存是正确的。
如果没有，您可能需要仔细检查ug332。
问候，
的Gabor
-  Gabor



以下为原文

One other question.  Are you using the SPI direct programming using the schematic from
ug332?  Or do you use the indirect SPI programming through the Spartan 3A JTAG?
 
If you use the indirect mode, then you can be fairly sure that your connections between the
FPGA and flash are correct.  If not, you may want to double check against ug332.
 
Regards,
Gabor
-- Gabor

当我的主板无法启动FPGA时，我讨厌它。
它简直太糟糕了。
我过去搞乱配置电路的地方是：
1. SPI_clock。
当从同一SPI NVRAM配置多个FPGA时，“主”FPGA和SPI NVRAM需要位于SPI_clock走线的两端。
如果“主”FPGA从中间驱动该网络，或者SPI NVRAM不在跟踪的末尾，那么时钟运行的反射可能会导致问题。
SPI_clock运行的并行终止总是一个好主意（您可以稍后解除它）。
如果您不想燃烧并联电阻的直流电源，则AC端接0.1uF电容（直流电源为零）。
2. M0 / M1 / M2下拉。
我忘记了我是否遇到过品牌A或品牌X FPGA的这个问题，但是这些引脚需要直接连接到GND才能“拉低”。
1K pulldown R在我的至少一个设计中不起作用，我从未重复过这个错误。
3.如果SPI网络上有多个丢包，请使用相当高带宽的探测器检查每次丢弃时的CLK与MISO数据时序（350MHz或更快是好的）。
检查有关捕获数据的重要（上升）时钟边沿的数据。
两个时钟边缘都“干净”且单调吗？
在时钟上升沿之前和之后，数据是否稳定，具有良好的电平？
4.您还必须在SPI NVRAM上具有良好的信号完整性和MOSI数据信号的时序。
FPGA必须将读地址发送到NVRAM，因此这很重要。
检查时钟边沿和MOSI数据建立/保持时间，直接在NVRAM上探测。
还有'同上'对Gabor的评论。
其他可能出错的是电源。
在配置过程中检查带有示波器的3.3V电源轨，看看是否有稳定的电平或任何下降（使用触发电平调节旋钮来查看任何毛刺有多低）。
有时在通电时，电源上的负载或毛刺不会通过下载电缆加载和验证NVRAM内容。
这里有一个线索：FPGA在上电时不会自动配置，但是如果你在上电后打开它的PROG *引脚就会配置它。
如果发生这种情况，则表明在开机时特别出现问题。
您可能需要一个延迟电路来延迟配置，直到电路板支付结束。
我确信这本书是一本FAQ本书。
当FPGA配置不起作用时，这是一种令人沮丧的可怕感觉，但是当你弄明白并修复它时，它确实感觉很好。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
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以下为原文

I hate it when my board doesn't boot the FPGA.  It just plain sucks.
 
Areas where I've messed up the config circuit in the past have been:
 
1.  SPI_clock.  When configuring multiple FPGAs from the same SPI NVRAM, the 'master' FPGA and the SPI NVRAM need to be at opposite ends of the SPI_clock trace.  If the 'master' FPGA is driving this net from the middle, or the the SPI NVRAM is not at the end of the trace, then reflections on the clock run can cause problems.  Parallel termination of the SPI_clock run is always a good idea (you can de-populate it later).  If you don't want to burn the DC power of parallel resistors, then AC couple the termination with 0.1uF caps (DC power is zero).
 
2.  M0/M1/M2 pulldowns.  I forget whether I had this problem with brand A or brand X FPGAs, but these pins need to be tied directly to GND for 'tie low'.  A 1K pulldown R did NOT work in at least one of my designs, and I never repeated THAT mistake.
 
3.  If you have multiple drops on the SPI nets, check CLK vs. MISO data timing at each drop with a decently high-bandwidth probe (350MHz or faster is good).  Check data with respect to the important (rising) clock edge for capturing the data.  Are both clock edges 'clean' and monotonic?  And is the data solidly stable, with good levels, before and after the rising clock edge ?
 
4.  You also have to have good signal integrity and timing for the MOSI data signal at the SPI NVRAM.  The FPGA must send the read address to the NVRAM, so this is important.  Check clock edges and MOSI data setup/hold time, probing directly at the NVRAM.
 
And 'dittoes' to Gabor's comments as well.
 
5.  Something else which can go wrong is the power supply.  Check the 3.3V supply rail with a scope during the config process, and see if you have solid levels or any dips (use the trigger level adjust knob to see just how low any glitches go).  Sometimes at power-on, there are loads or glitches on the power supply that don't show up using a download cable to load and verify NVRAM contents.  Here's a clue:  FPGA doesn't self-config at power up, but if you yank on its PROG* pin after powerup it configures.  If this happens, it's a sign of something amiss specifically at power-on time.  You may need a delay circuit to hold off configuration until after the board suppy has settled.
 
I'm sure this is a FAQ book subject all unto itself.  It's a horrible feeling of frustration when FPGA config doesn't work, but it sure feels good when you figure it out and fix it.
 
- Bob Elkind
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哎呀....
我在模式引脚上有一个外部10K下拉电阻，其强度不足以克服内部上拉。
现在我可以从SPI flash启动了。
感谢大家的“死机”建议。



以下为原文

Ooops....
 
I have an external 10K pulldown resistor on the mode pins, which is not strong enough to overcome the internal pullup.
Now I can boot from SPI flash.
 
Thanks everyone for the "dead-on" suggestions.
 
 
 
 
 

vohaid写道：
现在我可以从SPI flash启动了。
是时候打破香槟了！
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

 

vohaid wrote:
Now I can boot from SPI flash.

Time to break out the champagne!
 
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
vohaid写道：
现在我可以从SPI flash启动了。
是时候打破香槟了！
干杯!



以下为原文

eteam00 wrote:
 

vohaid wrote:
Now I can boot from SPI flash.

Time to break out the champagne!
 

Cheers!