ADC采样可以从I/O线中获得多少抖动

你好，
这可能是一个重复的问题，但我找不到这个问题的满意答案。
所以我在这里再次发布它。
当您从FPGA的时钟源开始对ADC进行采样时，我们可以从I / O线中获得多少抖动。
这对于我将要进行的测量的谐波平衡非常关键，因此非常感谢任何帮助。
在我计划使用的电路中，ADC芯片选择的下降沿异步启动ADC的采样，如果我从Spartan 3A FPGA驱动该CS信号，则采样中的抖动是多少。
或者，其中一位工程师建议我在极低的抖动时钟上使用外部D-FF IC运行，并将D输入连接到FPGA CS引脚，我已经附加了一个声明采用这种方法产生20 ps抖动的应用笔记。
我不确定它与FPGA驱动的解决方案有多么不同。
是否有额外的时钟或任何其他形式的抖动在FPGA中产生，这使得外部D-FF解决方案更好？
“http://cds.linear.com/docs/Datasheet/2355f.pdf第13页，最小化转换输入上的抖动。”



以下为原文

Hello,

This probably is a repeat question, but I could not find a satisfactory answer to this problem. So here I am posting it again.

When you start sampling an ADC from a clock source from FPGA, exactly how much jitter can we expect from the I/O lines. This is very critical for HARMonic Balance of the measurements I am going to make, so any help would be greatly appreciated.

In the circuit that I am planning to use, the falling edge of the Chip Select of the ADC asynchronously starts the sampling of the ADC, and if I drive this CS signal from a Spartan 3A FPGA, how much is the jitter in the sampling.
Alternatively, one of the engineers proposed that I use an external D-FF IC running on a extremely low jitter clock and the D input be tied to the FPGA CS pin, I have attached a application note claiming a 20 ps jitter by adopting this approach. I am not sure how different it is from an FPGA driven solution. Is there additional clock or any other form of jitter that gets produced in the FPGA which makes an external D-FF solution better?

"http://cds.linear.com/docs/Datasheet/2355f.pdf page 13, minimizing jitter on the conv input."