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大家好,我是Vittorio,我是FPGA和vhdl的初学者,我正在使用spartan3-e demoboard和digilent的Lcd。
我有这个问题,也许一些专家可以帮助我理解。 请参阅下面的代码如果输入引脚上的转换发生变化,我想驱动四个LED。 如果输入引脚为“1”,则如果输入引脚为“0”,则希望相继打开芯片1毫秒,并依次关闭所有LED。 我的问题是LED同时开启和关闭......这是什么交易? 先谢谢你。 图书馆IEEE; 使用IEEE.STD_LOGIC_1164.ALL; 使用IEEE.STD_LOGIC_ARITH.ALL; 使用IEEE.STD_LOGIC_UNSIGNED.ALL; ----如果实例化,则取消注释以下库声明 ----本代码中的任何Xilinx原语。 - 图书馆UNISIM; - 使用UNISIM.VComponents.all; 实体Powersequencer是 端口(VDDCHK:STD_LOGIC; CLK:在STD_LOGIC中; VDD:输入STD_LOGIC; VDDIN:输入STD_LOGIC; VH:inout STD_LOGIC; COMn:inout STD_LOGIC); 结束权力顺序; 建筑行为的力量序列是 开始 过程(CLK,VDDCHK) 开始 如果VDDCHK ='1'那么 VDD VDDIN VH COMn elsif VDDCHK ='0'然后 VDD VDDIN VH COMn结束if; 结束过程; 结束行为; 以上来自于谷歌翻译 以下为原文 Hello All, i'm Vittorio and i'm a beginner in fpga and vhdl, i'm using spartan3-e demoboard with Lcd from digilent. i have this issue and maybe some expert can help me to understand. pls see the code below i would like to drive four LED if a contition on the input pin change. If the input pin is "1" a would like turn on chip in sequence by 1millisecond from eachother and turn off all led in sequence if the input pin is "0". my problem is the LED turns on and off simultanusly... what's the deal? thank you in advance. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Powersequencer is Port ( VDDCHK : in STD_LOGIC; CLK : in STD_LOGIC; VDD : inout STD_LOGIC; VDDIN : inout STD_LOGIC; VH : inout STD_LOGIC; COMn : inout STD_LOGIC); end Powersequencer; architecture Behavioral of Powersequencer is begin process (CLK, VDDCHK) begin if VDDCHK='1' then VDD <='1' after 100 ms; VDDIN<='1' after 200 ms; VH<='1' after 300 ms; COMn<='1' after 400 ms; elsif VDDCHK='0' then VDD <='0' after 100 ms; VDDIN<='0' after 300 ms; VH<='0' after 200 ms; COMn<='0' after 100 ms; end if; end process; end Behavioral; |
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7个回答
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你的英雄绝对是正确的。
您必须考虑创建所需函数所需的硬件,然后编写代码以创建函数。 如果您想将信号延迟一段时间,那么您需要一个计数器来跟踪循环次数,并需要一个比较器来确定何时在正确的时间终止。 例如,如果你有一个10 MHz的时钟而你想要等待1秒,那么你需要数到1000万。 一本好的VHDL或Verilog(作为一个程序员,你可能会发现Verilog更易于使用)本书对于初学者和参考是必不可少的。 在这种情况下,你可以查找“after”关键字,它应该在文本中非常明显,这仅用于行为模拟。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Your insticts here are absolutely correct. You must think in terms of what hardware is necessary to create your desired function and then write your code to create the function. If you want to delay a signal by some amount of time then you need a counter to keep track of the number of cycles and a comparator to determine when the terminate at the correct time. For instance if you have a 10 MHz clock and you want to wait for 1 sec then you need to count to 10 million. A good VHDL or Verilog (as a programmer you may find Verilog far simpler to use) book is essential to have as a beginner and for reference. In this case, you could have looked up the "after" keyword and it should have been very obvious in the text that this was for behavioural simulation only. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
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是时候买一本合适的VHDL教科书了(我喜欢Ashenden;他应该寄给我一份第三版的副本,用于我为他做的所有先令)。
另外,请阅读XST用户指南,您将在其中了解合成时忽略“after”关键字。 为什么会被忽略? 认为硬件。 想想你将如何在硬件中构建这样的延迟。 -一个 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 Time to buy a proper VHDL textbook (I like Ashenden; he should send me a copy of the 3rd edition for all the shilling I do for him). Also, read the XST User Guide, where you will learn that the "after" keyword is ignored for synthesis. Why is it ignored? THINK HARDWARE. THINK about how you would build such a delay in HARDWARE. -a ----------------------------Yes, I do this for a living. |
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有人可以告诉我,如果我写的是不是公牛**。
因为我也发出一个警告信息,其中引脚时钟未完成。 警告:PhysDesignRules:367 - 信号不完整。 信号 不会在设计中驱动任何负载引脚。 真的很棒 维托里奥 以上来自于谷歌翻译 以下为原文 could somebody tell me if what i wrote over are bull**bleep** or not. pls because also i che a warning message where the pin clock is uncomplete. WARNING:PhysDesignRules:367 - The signal does not drive any load pins in the design. really appriciate Vittorio |
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是的,它是“公牛** ble **”。
请参阅bassman59之前的帖子 您收到的警告消息是正确的。 信号不会在代码中的任何位置使用。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Yes, it is "bull**bleep**". See the previous posting by bassman59 The WARNING message that you received is correct. The signal is not used anywhere in your code. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢你的回复,我的方面可以是一个简单的答案,专家说,维托里奥你必须考虑硬件,而不是软件,唯一的方法是使用计数器来计算时钟脉冲!
对不起,对于像我这样的初学者来说,这是一种灾难。 我擅长微芯片c编程这是我在vhdl的第一线。 我正在试图交换我的想法......请给我一个建议我,阅读一周的书籍和类似的东西,因为你是正常的vhdl verilog和一切,试着想象一下第一种方法....我 希望你能理解我此刻的坏感......维托里奥 以上来自于谷歌翻译 以下为原文 Thank you for reply, what i'm aspecting can be a simple answer where an expert say, Vittorio you must think in hardware and not anymore in software, the only way is to use a counter to count clock pulse! i'm sorry but for a beginner like me in vhdl is a kind of disaster. i'm skilled in microchip c programming this is my first lines in vhdl. I'm trying to exchange my mind... pls i need just a suggestion i', reading from a week books and stuff like that, for you is normal vhdl verilog and everything, try to immagine the first approach.... i hope you can understand my bad feeling at this moment... Vittorio |
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你的英雄绝对是正确的。
您必须考虑创建所需函数所需的硬件,然后编写代码以创建函数。 如果您想将信号延迟一段时间,那么您需要一个计数器来跟踪循环次数,并需要一个比较器来确定何时在正确的时间终止。 例如,如果你有一个10 MHz的时钟而你想要等待1秒,那么你需要数到1000万。 一本好的VHDL或Verilog(作为一个程序员,你可能会发现Verilog更易于使用)本书对于初学者和参考是必不可少的。 在这种情况下,你可以查找“after”关键字,它应该在文本中非常明显,这仅用于行为模拟。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Your insticts here are absolutely correct. You must think in terms of what hardware is necessary to create your desired function and then write your code to create the function. If you want to delay a signal by some amount of time then you need a counter to keep track of the number of cycles and a comparator to determine when the terminate at the correct time. For instance if you have a 10 MHz clock and you want to wait for 1 sec then you need to count to 10 million. A good VHDL or Verilog (as a programmer you may find Verilog far simpler to use) book is essential to have as a beginner and for reference. In this case, you could have looked up the "after" keyword and it should have been very obvious in the text that this was for behavioural simulation only. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢你现在的确切解释我很满意。
非常感谢你...我保证我会继续阅读烹饪书......欢呼维托里奥 以上来自于谷歌翻译 以下为原文 thank you for the exact explenation now i'm satisfy. thank you so much ... i promise i continue to read cook book...... cheers vittorio |
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