需要有关带有DCM的Spartan 3A FPGA的帮助

大家好，
我是使用Xilinx ISE和编程FPGA的新手。
我开发了一个程序来模拟DDR SDRAM用于测量目的。
我使用了许多原语，如Blockram（IP CORE gen工具），DCM，ODDR2的IDDR2等。
我已经生成了编程文件，我正在使用使用Platform Flash的MAster Serial Mode来编程我的FPGA。
一切顺利，甚至Done引脚也很高兴。
但问题是：
1.当我使用DCM时，我没有看到PLL锁定引脚变高，所以为了确保FPGA被编程，我只是为几个测试信号分配了逻辑'1'，并尝试在示波器上探测它们，
但他们也没有表现出活动，他们都仍然是逻辑'0'。
2.我相信我已经提供了所有关于我想要监控的引脚的净LOC约束，但是我也没有看到任何活动。
3.另一件事是，当我在我的设计上应用定时限制（200 Mhz）时，它说时序约束不能匹配“你的设计中有2个失败的约束”，我还没有处理。
4.所以作为一个主要问题，我需要帮助看看我的FPGA上的一些活动，特别是DCM输出。
我请求那里的天才帮助我。
任何信息都受到高度赞赏。
谢谢＆amp;
问候，
沙克蒂。



以下为原文

Hello Everyone,

I am a newbie at using the Xilinx ISE and programing FPGA's. I have developed a program to emulate a DDR SDRAM  for measurement purpose. I have used a number of primitives like Blockram (IP CORE gen tool), DCM, ODDR2's IDDR2's, etc.
I have generated the progrmaming file and I am using MAster Serial Mode using Platform Flash to program my FPGA.
Everything goes well and even the Done pin goes hign.

But the Problem is:
1. I dont see the PLL locked pin go high as I am using the DCM, so to make sure that the FPGA is programmed, I just assigned logic '1' to a couple of test signals and tried to probe them on the scope, but they too show no activity, they all are still logic '0'.

2. I believe that I have provided all the net LOC constraints on alll my pins I want to monitor, but then too I dont see any activity.

3. Well an other thing is that when I apply timing constratint (200 Mhz) on my design it says that the timing constraints cant be matched "There are 2 failing constraints in your design", I am yet to deal with that.

4. So as an primamry issue, I need help to see some activity on my FPGA escpecially the DCM output.

I request the geniuses out there to kindly help me. Any piece of information is highly appreciated.

Thanks & Regards,

Shakti.