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嗨,我想用ADS发布SiP文件的布局SI。
如果有人可以通过一步一步的程序帮助我处理Cadence,然后进入ADS,那将是很棒的。 我特别关注设置。 例如,如何/如何设置正确的层叠和正确的芯片叠加,以便ADS在导入时不会出现任何错误。 我在SiP和ADS中都安装了ial工具。 我可以打开并导出sip文件和广告文件。 但是,在SiP编辑器中生成广告文件时,它会发出许多警告,例如许多键合线未被翻译和忽略。 我想我没有正确设置SiP文件,这就是它给出错误的原因。 因此,我正在寻找一步一步的文件。 随之而来的是我想要一些文件来详细了解ADS中盖板和槽的概念。 和ADS中的基本设置文档类似于SiP中的文档。 谢谢Ajay 以上来自于谷歌翻译 以下为原文 Hi, I want to do post layout SI of SiP File using ADS. It would be great if someone could help me with a document with the step by step procedure to follow into Cadence and then into ADS. I am particularly looking at setup. for example how/what to setup proper layer stack up and proper die stack up in cadence so that ADS doesn't give any error while importing. I have installed the ial tool in both SiP and ADS. and I am able to open and export the sip file and ads file. But while generating ads file in SiP editor it's giving many warnings like many bondwires are not translated and ignored. I guess that I am not setting up the SiP file properly that's why it's giving error. Hence I am looking for a step by step document. Alongwith that I want some document to understand the concept of cover plate and slot in ADS in detail. and the basic setup document in ADS similar to the one in SiP. Thanks Ajay |
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您好,Agilent EEsof知识中心提供的Allegro ADFI Tutorial Presentation幻灯片可能会对您有所帮助。
以下是知识中心文章的链接以及下载演示文稿的链接:http://edocs.soco.agilent.com/display/eesofkcads/Allegro+ADFI+Tutorial+Presentation 以上来自于谷歌翻译 以下为原文 Hello, There is an Allegro ADFI Tutorial Presentation slide set in the Agilent EEsof knowledge center that may be helpful. Here is the link to the Knowledge center article and the link to download the presentation: http://edocs.soco.agilent.com/display/eesofkcads/Allegro+ADFI+Tutorial+Presentation |
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