使用PLL生成时钟

根据我的理解，您使用Dcm（数字时钟管理器）或MMCM（混合模式时钟管理器）从fpga内部的PLL创建了一个时钟。
通常你有一些时钟输入到fpga说1 MHz，你想要一个8 MHz时钟用于你的自定义逻辑/外部dac。
您将它通过MMCM / DCM（PLL）传递给时钟多达8位。您现在拥有8 MHz时钟的PLL输出。
这真的取决于你的设计条目（你使用的是块设计还是纯VHDL？）但是我们来谈谈vhdl。
处理（clk_8MHz）
开始
if（falling_edge（clk_8MHz））然后 - 这将在Clk_8MHz的下降沿采样所有寄存器/触发器 
dac_clk
处理（clk_8MHz）
开始
if（falling_edge（clk_8MHz））然后 - 这将在Clk_8MHz的下降沿采样所有寄存器/触发器 
万一;
结束过程;
如果这不起作用，那么很可能其他东西不起作用。
您可以使用Vivado逻辑分析器/芯片示波器来查看信号或使用示波器测量dac输入引脚上的dac时钟。
（取决于您的PCB（印刷电路板）是否有探测访问权限。
当你说你希望它同步时，我显示的方式是同步的，因为你对dac和自定义逻辑使用相同的时钟。
当您将信号拉出过程块时，假设您现在正在构建电线而不是触发器。
在原帖中查看解决方案



以下为原文

From my understanding you created a clock from a PLL inside the fpga using a Dcm(digital clock manager) or MMCM(Mixed mode clock manager).
 
Usually you have some clock input into the fpga say 1 MHz and you want a 8 MHz clock for your custom logic/External dac.  You pass it through the MMCM/DCM (PLL) to mulitply the clock by 8.  Output of the PLL you now have a 8 MHz clock. 
 
It really depends on your design entry (are you using block design or pure VHDL?)  but lets talk about vhdl.
 
process(clk_8MHz)
begin
if(falling_edge(clk_8MHz)) then  -- This will sample all registers/flip flops at the Falling edge of Clk_8MHz
   dac_clk <= clk_8MHz;  -- This will set DAC_clk as the current value of CLK_8MHz (which can be either a zero or 1 or metastability even can happen since you are sampling the clock right in the middle of falling edge.  So This should not work properly.
end if;
end process;
 
 
---- Instead of you want to pass a clock properly you bring it out of the process block.  The exact same clock that was sent to your custom IP is now sent to dac_clk.  
 
 dac_clk <= clk_8MHz;
process(clk_8MHz)
begin
if(falling_edge(clk_8MHz)) then  -- This will sample all registers/flip flops at the Falling edge of Clk_8MHz
   
end if;
end process;
 
If this doesn't work than it is most likely that something else is not working.  You can use Vivado logic analzyer/chip scope to take a look at the signal or use an oscilloscope to measure the dac clock on the input pin of your dac.  (Depends if you have probing access on your PCB (printed circuit board).
 
When you say you want it synchronous the way I shown is synchronous since you are using the same clock for both the dac and custom logic.  
 
When you pull the signal out of the process block assume that you are now building a wire instead of a flip flop.  
View solution in original post

你好@ enslaved46
由于您要将时钟转发出FPGA，因此建议使用ODDR进行时钟转发。
看起来您正在使用ILA探测PLL输出。
如果是这种情况，请确保连接到调试集线器的时钟是PLL输出的2倍。
你使用的是哪种设备？
还有Vivado版？
你运行模拟并观察到相同的行为吗？
谢谢，
维奈
--------------------------------------------------
------------------------------------------您是否尝试在Google中输入问题？
？
如果没有，你应该在发布之前。
此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。



以下为原文

Hi @enslaved46
 
Since you are forwarding the clock out of FPGA, it is recommended to use ODDR for clock forwarding.
It looks like you are probing the PLL output using ILA. If this is the case, make sure the clock connected to debug hub is 2x of PLL output.
 
Which device are you using? Also Vivado version??
Did you ran the simulation and observed same behavior?
 
Thanks,
Vinay
--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

@vuppala感谢您的努力。
我正在使用Vivado 2016.1版本的ZED板和LTC 1668 DAC。
我解决了这个问题，它与PS部分有关。
如果信号频率发生变化，则每次都需要复位DAC。
DAC的这个属性我没有意识到。
最后一点是使用ODDR时钟转发的原因是什么。
我在网上阅读了一些有关ODDR的内容，并表示它可以改善输出时钟的不确定性。
我还缺少ODDR的其他东西吗？
谢谢



以下为原文

@vuppala Thank you for your effort. I am using Vivado 2016.1 version for ZED board and LTC 1668 DAC.
I solved the issue, it was with the PS part. The DAC needs to be reset every time if frequency of the signal is being changed. This property of DAC I was unaware of.    
One last thing is that what is the reason behind using ODDR clock forwarding. I read some stuff online regarding ODDR and it says it improves the uncertainty of the output clock. Any thing else I am missing for ODDR?
Thank you

你好@ enslaved46
你是对的。
使用ODDR转发时钟可以改善输出时钟的不确定性。
谢谢，
维奈
--------------------------------------------------
------------------------------------------您是否尝试在Google中输入问题？
？
如果没有，你应该在发布之前。
此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。



以下为原文

Hi @enslaved46
 
You are correct.
forwarding the clock using ODDR improves the uncertaining of the output clock.
 
Thanks,
Vinay
--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

嗨，
我不明白你为什么要使用一个进程传递时钟？
从你的vhdl的外观来看，这将无法正常工作。
如果要为逻辑使用完全相同的时钟并将其发送到外部dac，则需要将该分配带到进程块之外。
如果你测量了dac上的时钟，我相信你会看到亚稳态问题或者它停留在0。



以下为原文

Hi,
 
I do not understand why you are passing the clock using a process??
From the look of your vhdl that will not work properly.
 
If you want to use the exact same clock for the logic and send it to an external dac, you want to bring that assignment outside of the process block.  If you measured the clock on the dac I am sure you would either see metastability problems or it stuck at 0.

@csholikowski感谢您的评论。
我使用一个进程来安排它的同步。
我试图在这个过程之外做这个并且时钟没有滴答作响。
这就是我把它放在里面的原因，它在某种程度上起作用。
你能告诉我它是如何以正确的方式完成的。
谢谢。



以下为原文

@csholikowski Thanks for the comment. I am passing the clock using a process to make it synchronous. I tried to do it outside the process and got clock was not ticking. That's the reason I put it inside and it somehow worked. Could you show me how it's done in proper way. Thank you.

还要锁定clockasoutput时钟



以下为原文

also to latch the clock as output clock

根据我的理解，您使用Dcm（数字时钟管理器）或MMCM（混合模式时钟管理器）从fpga内部的PLL创建了一个时钟。
通常你有一些时钟输入到fpga说1 MHz，你想要一个8 MHz时钟用于你的自定义逻辑/外部dac。
您将它通过MMCM / DCM（PLL）传递给时钟多达8位。您现在拥有8 MHz时钟的PLL输出。
这真的取决于你的设计条目（你使用的是块设计还是纯VHDL？）但是我们来谈谈vhdl。
处理（clk_8MHz）
开始
if（falling_edge（clk_8MHz））然后 - 这将在Clk_8MHz的下降沿采样所有寄存器/触发器 
dac_clk
处理（clk_8MHz）
开始
if（falling_edge（clk_8MHz））然后 - 这将在Clk_8MHz的下降沿采样所有寄存器/触发器 
万一;
结束过程;
如果这不起作用，那么很可能其他东西不起作用。
您可以使用Vivado逻辑分析器/芯片示波器来查看信号或使用示波器测量dac输入引脚上的dac时钟。
（取决于您的PCB（印刷电路板）是否有探测访问权限。
当你说你希望它同步时，我显示的方式是同步的，因为你对dac和自定义逻辑使用相同的时钟。
当您将信号拉出过程块时，假设您现在正在构建电线而不是触发器。



以下为原文

From my understanding you created a clock from a PLL inside the fpga using a Dcm(digital clock manager) or MMCM(Mixed mode clock manager).
 
Usually you have some clock input into the fpga say 1 MHz and you want a 8 MHz clock for your custom logic/External dac.  You pass it through the MMCM/DCM (PLL) to mulitply the clock by 8.  Output of the PLL you now have a 8 MHz clock. 
 
It really depends on your design entry (are you using block design or pure VHDL?)  but lets talk about vhdl.
 
process(clk_8MHz)
begin
if(falling_edge(clk_8MHz)) then  -- This will sample all registers/flip flops at the Falling edge of Clk_8MHz
   dac_clk <= clk_8MHz;  -- This will set DAC_clk as the current value of CLK_8MHz (which can be either a zero or 1 or metastability even can happen since you are sampling the clock right in the middle of falling edge.  So This should not work properly.
end if;
end process;
 
 
---- Instead of you want to pass a clock properly you bring it out of the process block.  The exact same clock that was sent to your custom IP is now sent to dac_clk.  
 
 dac_clk <= clk_8MHz;
process(clk_8MHz)
begin
if(falling_edge(clk_8MHz)) then  -- This will sample all registers/flip flops at the Falling edge of Clk_8MHz
   
end if;
end process;
 
If this doesn't work than it is most likely that something else is not working.  You can use Vivado logic analzyer/chip scope to take a look at the signal or use an oscilloscope to measure the dac clock on the input pin of your dac.  (Depends if you have probing access on your PCB (printed circuit board).
 
When you say you want it synchronous the way I shown is synchronous since you are using the same clock for both the dac and custom logic.  
 
When you pull the signal out of the process block assume that you are now building a wire instead of a flip flop.  

@csholikowski非常感谢你！
现在我明白了差异!!
:)



以下为原文

@csholikowski Thank you very much!! Now I understand the difference!! :)