@always (posedge clk ) /*clk为FPGA工作时钟。
if(rst && USB_RXF==0)
begin
case(Rstate)
Rstate0:
begin
USB_RD<=0; /*产生读信号的下降沿
Rstate<=Rstate1;
end
Rstate1:
begin
RframeBuf[Rpointer]<=USB_DATA; /*读FT245BM芯片FIFO的当前字节
Rstate<=Rstate2;
end
Rstate2:
begin
if(Rpointer== FrameLen-1) /*如果已经接收到完整的一帧,则转Rstate3,
begin
Rstate<=Rstate3;
Rpointer<=0;
end
else /*一帧未接收完,转Rstate0继续接收
begin
Rstate<=Rstate0;
Rpointer<=Rpointer+1;
end
USB_RD<=1;
end
Rstate3: /*处理收到的帧
begin
Rstate<=Rstate0;
/*在此添加处理帧的代码,本文略*/
end
end
else
begin
Rstate<=Rstate0;
USB_RD<=1;
End