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根据一些WP文档,最佳编码实践不是尽可能使用全局重置?
这里有一个问题,如果没有复位引脚,如何复位FPGA,每次想要复位时都要关闭FPGA! 以上来自于谷歌翻译 以下为原文 According to some WP documents , the best coding practice is not using global reset as possible ? Here comes the question , how to reset the FPGA ,if there is no reset pin , Power down the FPGA every time i want to reset ! |
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3个回答
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在许多系统中,复位仅使用一次 - 上电时。
对于这些系统,系统可以设计为没有(或最小)显式上电复位,因为FPGA在其配置周期期间已经初始化。 如果您的系统确实需要在用户控制下返回到重置状态,那么您有两个选项(除了关闭FPGA之外)。 - 通过拉动PROG_B引脚重新启动配置过程 - FPGA将完全重新初始化,重新下载其bistream,因此将返回到比特流中包含的“INIT”状态 - 实现全局重置结构 针对全局复位的建议专门针对仅使用全局复位作为上电复位的设计。 如果您需要经常重置设计,请执行全局重置。 但是,请注意,这会在FPGA内部产生大量额外的布线资源,并且会对您可以运行设计的最大频率产生负面影响。 如果您愿意为快速重置设计的能力支付这些价格,那么您应该实现所需的重置。 顺便说一句,必须小心地完成“无全局重置”的建议。 在大多数系统中,至少有少数FF必须同步复位才能使系统正常复位。 要正确识别那些必须从那些不需要重置的东西,这可能是一个挑战。 Avrum 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 In many systems, the reset is used only once - on power up. For these systems, systems can be designed with no (or minimal) explicit power-on reset, since the FPGA is already initialized during its configuration cycle. If your system does have a need to be returned to the reset state under user control, then you have two options (other than powering down the FPGA). - re-start the configuration process by pulling the PROG_B pin - the FPGA will completely re-initialize, re-download its bistream, and hence will return to the "INIT" state contained in the bitstream - implement a global reset structure The recommendation against global resets is specifically aimed at the design that only uses the global reset as power-on reset. If you need to reset the design often, then implement a global reset. But, be aware that this costs significant additional routing resources inside your FPGA, and can have a negative impact on the maximum frequency you can run your design at. If you are willing to pay these prices for the ability to reset your design quickly, then you should implement the reset you want. And, by the way, the recommendation of "no global reset" must be done carefully. In most systems there are at least a handful of FFs that must be reset synchronously for the system to come out of reset properly. It can be a bit of a challenge to correctly identify those that must be reset from those that don't need to. Avrum View solution in original post |
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在许多系统中,复位仅使用一次 - 上电时。
对于这些系统,系统可以设计为没有(或最小)显式上电复位,因为FPGA在其配置周期期间已经初始化。 如果您的系统确实需要在用户控制下返回到重置状态,那么您有两个选项(除了关闭FPGA之外)。 - 通过拉动PROG_B引脚重新启动配置过程 - FPGA将完全重新初始化,重新下载其bistream,因此将返回到比特流中包含的“INIT”状态 - 实现全局重置结构 针对全局复位的建议专门针对仅使用全局复位作为上电复位的设计。 如果您需要经常重置设计,请执行全局重置。 但是,请注意,这会在FPGA内部产生大量额外的布线资源,并且会对您可以运行设计的最大频率产生负面影响。 如果您愿意为快速重置设计的能力支付这些价格,那么您应该实现所需的重置。 顺便说一句,必须小心地完成“无全局重置”的建议。 在大多数系统中,至少有少数FF必须同步复位才能使系统正常复位。 要正确识别那些必须从那些不需要重置的东西,这可能是一个挑战。 Avrum 以上来自于谷歌翻译 以下为原文 In many systems, the reset is used only once - on power up. For these systems, systems can be designed with no (or minimal) explicit power-on reset, since the FPGA is already initialized during its configuration cycle. If your system does have a need to be returned to the reset state under user control, then you have two options (other than powering down the FPGA). - re-start the configuration process by pulling the PROG_B pin - the FPGA will completely re-initialize, re-download its bistream, and hence will return to the "INIT" state contained in the bitstream - implement a global reset structure The recommendation against global resets is specifically aimed at the design that only uses the global reset as power-on reset. If you need to reset the design often, then implement a global reset. But, be aware that this costs significant additional routing resources inside your FPGA, and can have a negative impact on the maximum frequency you can run your design at. If you are willing to pay these prices for the ability to reset your design quickly, then you should implement the reset you want. And, by the way, the recommendation of "no global reset" must be done carefully. In most systems there are at least a handful of FFs that must be reset synchronously for the system to come out of reset properly. It can be a bit of a challenge to correctly identify those that must be reset from those that don't need to. Avrum |
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是。
fpgas加电到一个已定义的状态, 如果你需要重置,你可以将它编码到你的代码中, 放入重置然后添加额外的路由, 如此典型,你只能重置你需要的东西, 以上来自于谷歌翻译 以下为原文 yes. fpgas power up into a defined state, if you need reset, you code it into your code, putting in reset then adds extra routing, so typiclay you only reset what you need to, |
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