Spartan-6 FPGA是否需要设计中的上电复位电路

您好Xilinx社区，
有人能否就Spartan-6 FPGA是否需要设计中的上电复位电路给出明确的答案？
在附图中，我们的设计中有这个上电复位电路。
然而，我们遇到了电路问题，并决定在我们的设计中将它们全部移除。
我们只是想确保通过这样做，我们没有采用基于Spartan-6的设计的重要电路。
此上电复位电路的目的是在它监控的两个电源中的任何一个时提供复位信号：+ 3.3V和+ 1.2V或者FPGA本身的VCCINT和VCCO / VCCAUX电源低于a
某个门槛。
来自此上电复位电路的复位信号与FPGA固件中的DCM相连。
通过在我们的设计中移除此上电复位电路，我们基本上将DCM模块作为固件中的独立模块。
就我们已经看到Xilinx或Avnet的Spartan-6的几个评估卡的原理图而言，他们的设计中没有上电复位电路。
Xilinxs附带的示例Spartan-6原理图。
这是否意味着，在基于Spartan-6的设计中，真的不需要上电复位电路？
任何人都可以确认一下吗？
非常感谢你。
最好的祝福，
- 王牌
上电复位CIRCUIT.pdf 175 KB
xtp067_sp605_schematics.pdf 1305 KB



以下为原文

Hi Xilinx Community,

Can somebody please give a definitive answer to whether Spartan-6 FPGA's requires a Power On Reset circuit in the design?
In the attached schematics, we have this Power On Reset circuit in our design. However we have encountered issues with the circuit and have decided to remove it all together in our design. We just want to make sure that by doing this, we are not taking out an important circuit of a Spartan-6 based design.

The purpose for this Power On Reset circuit is that it provides a reset signal in the event that any of the two power supplies it monitors: +3.3V and +1.2V or the VCCINT and VCCO/VCCAUX supplies of the FPGA itself goes below a certain threshold. The reset signal coming from this Power On Reset circuit is tied to the DCM in the FPGA firmware. By removing this Power On Reset circuit in our design, we are basically making the DCM module as a standalone module in the firmware.

In so far as we have seen of the schematics of several evaluation cards for Spartan-6 by Xilinx or by Avnet, there are no Power On Reset circuit in their designs. Example Spartan-6 schematics by Xilinxs attached.

Does this mean then that, a Power On Reset circuit is NOT really needed in a Spartan-6 based design? Can anybody please confirm this? Thank you very much.

Best Regards,
-- ace            POWER ON RESET CIRCUIT.pdf ‏175 KB                xtp067_sp605_schematics.pdf ‏1305 KB