请问DDS ip是否允许控制生成波形的相移？

ug472详细介绍了如何使用MCMM提供静态或动态相移，
Zynq是一个7系列器件，因此可编程逻辑具有MMCM模块供您使用。
输出频率几乎相同的相位将是等时的。
几乎相同频率的输出频率将是等时的。
同相输出是同步的。
具有不同相位的相同频率的输出是合成的。
（我去了NIST博尔德时间学校...）
世界时间Stratum 1参考是等时的：许多时钟，几乎相同的频率（都在~1E-11之内）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

ug472 details how one uses the MCMM to provide static, or dynamic phase shift,
 
Zynq is a 7-series device, so the programmable logic has MMCM blocks for you to use.
 
Output frequencies almost the same phase would be isochronous.
 
Output frequencies almost the same frequency would be isotonous.
 
Outputs in phase are synchronous.
 
Outputs at the same frequency, with differing phases are syntonous.
 
(I went to the NIST Boulder Time School...)
 
The world time Stratum 1 reference is isochronous:  many clocks, almost the same frequency (all within ~1E-11).
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

很有意思 ：）
我忘了提到我需要将波形输出到外部引脚。
MCMM块的使用实际上是否可行？
有没有其他方法可以生成具有运行时可控相移的波形，例如通过DDS IP？
对不起，我是这个话题的新手。
谢谢！



以下为原文

Very interesting :)
 
I forgot to mention that I need to output the waveforms to external pins. 
Is the use of MCMM blocks actually feasible? Is there any other way to generate the waveforms with runtime controllable phase shift, for instance by means of the DDS IP?
Sorry I am a newbie on the topic.
Thank you!

一个，
什么频率范围？
MCMM最适合于具有已知方波相位关系的频率的简单任务。
直接数字频率合成（DDFS）是一种创建数控振荡器的方法，但这就是频率合成（任何频率从DDFS时钟的0到1/2）。
DSP48模块是一个很棒的DDFS相位累加器元件（DDFS的核心）。
DDFS方波输出是MSB，并且将具有1个时钟的非时间抖动，这可能是不可接受的。
然而，该抖动可以由PLL过滤。
对于低于DDFS输入范围的频率，可以设计合成器，通过在计数器中设置不同的复位值，以固定相位创建波形。
数字信号可以指向输出引脚。
可以使用输出引脚输出时钟，用于时钟转发，它使用IOB中的ODDR功能。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

a,
 
What range of frequencies?
 
The MCMM is best suited for the simple task of frequencies with known phase relationships for square waves.
 
Direct digital frequency synthesis (DDFS) is a way of creating a numerically controlled oscillator, but that is frequency synthesis (any frequency from >0 to 1/2 the clock of the DDFS).  The DSP48 blocks makes a great DDFS phase accumulator element (the heart of a DDFS).  DDFS square wave output is the MSB, and will have 1 clock unti time jitter, which may not be acceptable.  That jitter may be filtered by a PLL, however.
 
For frequencies below the input range for the DDFS, one may design a synthesizer to create waveforms at fixed phases by setting different reset values in counters.
 
Digital signals may be directed to output pins.  Clocks may be output by using an output pin for clock forwarding, which uses the ODDR capability in the IOB.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

频率应该是2 Mhz（可能更高，但现在让我们专注于此）。
使用DDS可以达到的相位分辨率是多少？
我的意思是，我可以达到1度相移分辨率吗？
如何减少1个时钟周期的抖动？
给定2 Mhz频率，您会使用DDS还是通过专用计数器实现该功能？
谢谢



以下为原文

Frequency should be 2 Mhz (maybe higher but lets concentrate on this for now).
Which is the phase resolution I could reach by using DDS? I mean, can I reach a 1 degree phase shift resolution ? How can I reduce the 1 clock period jitter? 
Given the 2 Mhz frequency, would you use the DDS or implement the function by means of dedicated counters?
thank you

一个，
DDFS不适合0.1度相位分辨率，控制和低抖动。
DDFS在频率分辨率方面具有广泛的任意精度，但是必须消除我难以实现的抖动（滤波器）。
频率范围是多少？
从0到2 MHz？
2 MHz +/- ??
赫兹
Austin Lesea主要工程师Xilinx San Jose



以下为原文

a,
 
DDFS would not be well suited to 0.1 degree phase resolution, control, and low jitter.
 
DDFS is great for a wide range to arbitrary accuacy in frequency resolution, but one has to remove the jitter (filter) which my be difficult.

What is the range of frequencies? from near 0 to 2 MHz?
 
2 MHz +/- ?? Hz
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢奥斯汀，
所需的相位分辨率为1度，你写道DDFS不适合0.1度相位分辨率，它是错误的还是你真的意味着0.1度？
如果是这样，1度是否可行？
初始应用中的频率范围为2Mhz +/- 200Khz。
（但是，在未来，频率可能会变得更高，高达30 Mhz ......但是现在我需要检查2 Mhz频率可以做什么）。
另外，如何使用DDFS估算出我期望的抖动？
由于内部时钟“限制”或由于DDFS行为，它实际上是一个时钟周期吗？
我的意思是，我可以为DDFS提供外部“低抖动”时钟源，以减少输出波形中的抖动吗？
非常感谢你
一个。



以下为原文

Thank you Austin,
required phase resolution would be 1 degree, you wrote that DDFS would not be suited for 0.1 degree phase resolution, was it a mistype or did you actually mean 0.1 degree? If so, would 1 degree be feasible instead?
The frequency range in the initial application would be 2Mhz +/- 200Khz. (but, in the future, frequency could become much higher, up to 30 Mhz... but for now I need to check what can be done with a 2 Mhz frequency). 
Also, how can I estimate the jitter that I should expect by using DDFS? Is it actually one clock period due to the internal clocks "limitations" or due to DDFS behaviour? I mean, could i provide an external "low jitter" clock source to the DDFS in order to reduce the jitter in the output waveforms?
Thank you very much
a.

一个，
听起来像电信同步应用程序。
为此，我使用了时钟频率为50 MHz的DDFS（从铷原子钟振荡器的原生时钟开始运行）。
然后，DDFS的MSB通过一个100K电阻器到达LC槽。
这辆坦克的Q值> 100。
通过快速比较器通过另一个100K电阻器采样槽以获得方波（Xilinx FPGA的IOB可以这种方式使用，因为它具有用于SSTL，HSTL或LVDS标准的出色比较器）。
可以使用VCXO代替LC储罐，但LC储罐便宜得多。
产生的抖动是不可测量的（在0到时钟频率的带宽中测得的0.01 UI以下）。
我使用了48位累加器，因此频率步长为3.5E-15。
由于设置（48位控制）设置频率而不是相位，因此未实现相位控制。
可以采用MSB并将其传递通过多个MMCM以实现所需的相移，然后传递给电阻器，并通过电阻器传输到比较器。
0.1度非常紧。
那是138皮秒。
旧产品中DCM的步长​​为~35 ps，MCM中的PLL是连续的（无步骤），但存在相位控制值，我相信为0到255（360度为256步）。
这不符合您的控制要求（您的是1/3600）。
那么，我该怎么做呢？
我会相移DDFS源时钟（现在你需要为不同相位的每个输出都有一个DDFS）。
在更高的频率下，相移步长和分辨率现在满足要求，但仍然存在如下问题：是否需要将任何相位设置为0到360度（不能仅在源时钟上完成DDFS）。
仍然需要为每个恢复的DDFS去抖动输出进行相移。
这意味着您具有精细相位和粗调相位调整功能。
选择DDFS时钟的频率，使两个调整course.fine有点排队意味着一点铅笔和纸张时间，看看你得到什么控制，在哪里。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

a,
 
Sounds like a telecom sync application.
 
For that I had used a DDFS clocked at 50 MHz (ran from the native clock of a rubidium atomic clock oscillator).

The MSB of the DDFS then went through a 100K resistor to a LC tank.  The Q of this tank was >100.  The tank is sampled through another 100K resistor by a fast comparator to derive a square wave (the IOB of the Xilinx FPGA may be used in this fashion as it has an excellent comparator for SSTL, HSTL or LVDS standards).  A VCXO could be used instead of the LC tanks, but the LC tanks are much less expensive.
 
The resultant jitter was immeasurable (below 0.01 UI measured in the bandwidth of 0 to the clock frequency).  I used a 48 bit accumulator, so the frequency step was 3.5E-15.
 
Phase control is not realized, as the setting (48 bit control) sets the frequency, not the phase.

One could take the MSB and pass it through more than one MMCM for the desired phase shift, and then to the resistors, and tanks through resistors to comparators.
 
0.1 degree is very tight.  That is 138 picoseconds.  The step size of the DCM in older products was ~35 ps, and the PLL's in the MCM are continuous (no step), but there is a phase control value, which I believe is 0 to 255 (256 steps for 360 degrees).
 
That does not meet your requirement for control (yours is 1/3600).
 
So, how would I do it?  I would phase shift the DDFS source clock (now you need a DDFS for every output of different phase).  At the higher frequency, the phase shift step and resolution now meets what is needed, but there is still the issue of if you need to set any phase from 0 to 360 degrees (cannot be done on the source clock to DDFS alone).
 
Still need a phase shift for each recovered DDFS de-jittered output.  This means you have a fine phase, and a coarse phase adjust capability.  Choosing the frequency for the DDFS clock such that the two adjustments course.fine somewhat line up means a little bit of pencil and paper time, looking at what control you get, where.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose