怎么将FIFO ADDR从EP6切换到EP2

如果您试图访问空的端点，那么您将无法在总线上得到任何东西。如果您没有实现流控制，那么端点缓冲区是否会在访问周期的中间填充。然后你将从FX2LP部分读取数据，这会使你失去同步。
你为什么要做这样的事？
当做，
阿南德



     以下为原文
  If you try to access the endpoint which is empty then you won't get anything on the bus. In case you're are not implementing flow control then if the endpoint buffer gets filled in the middle of your access cycle. Then you're going to partially read data from FX2LP which will make you lose sync.
    Why would you want to do something like this?
    Regards,
    Anand

谢谢阿南德。我在PC端有两个线程，一个线程连续地从EP6获取数据，每次使用异步数据传输（开始/等待/完成）获得20000个字节。另一个线程连续输出数据到EP2，每次使用异步数据传输（开始/等待/完成）输出20000个字节。在FPGA方面，有两个双缓冲数据缓冲器，一个用于数据采集（EP6）的具有20000个X2字节，一个用于数据输出（EP2）的只有1024×2字节。两个数据缓冲器都以一定的采样速率时钟输入/输出。问题是，我不能等待EP6完成20000字节的前向切换到EP2，否则连续的输出流将被中断，因为EP2的缓冲区尺寸比EP6的缓冲区小很多。因此，我想在FPGA中设计一个控制器，它分配时隙（比如说1000个IFCK周期）到输入流和输出流，而不检查EP6中的数据是否已被提交，EP2中的数据已经被读取或读取。它又得到了时隙。



     以下为原文
  Thanks Anand. I have two threads on PC side, one thread acquires data from EP6 continously, each time acquires 20000 Bytes using asynchronous data transfer (Begin/Wait/Finish). The other thread output data to EP2 continously, each time outputs 20000 Bytes using asynchronous data transfer (Begin/Wait/Finish). On the FPGA side, there are two double-buffered data buffers, the one for data acquisition (EP6) has 20000 x2 bytes, the one for data output (EP2) has only 1024 x 2 bytes. Both data buffers are clocked to input / output at certain sampling rates.  The problem is that I cannot wait for EP6 to complete 20000-Byte transfer before switching to EP2, otherwise the continous output stream will be interrupted because the buffer size for EP2 is much smaller than the buffer size for EP6. Therefore I want to design a controller in FPGA which allocates time slots (say 1000 ifclk cycles) to the input stream and output stream without checking whether the data in EP6 has been committed or not, and the data in EP2 has been read or not. I guess the input/output stream will recover seamlessly after the it gets the time slot again.