使用时钟信号驱动FF的CE引脚并启用FIFO的线路

arvindnr写道：
嘿大家，
快速威廉希尔官方网站 问题：
我一直在阅读有关同步设计实践的一些内容，并试图在我的设计中实现这些想法。
我想知道使用时钟信号驱动触发器的CE引脚是否是一个很好的设计实践？
不，因为全球时钟网仅用于时钟负载而不是触发器的CE引脚。
你会收到路由错误。
但是，您可以使用逻辑来驱动BUFG的CE输入，以便从该BUFG到其负载的时钟将根据您的需要启用。
----------------------------是的，我这样做是为了谋生。
在原帖中查看解决方案



以下为原文

arvindnr wrote:
Hey every one,

Quick technical question :
 
I have been reading a bit about synchronous design practices and trying to implement those ideas in my design. I wanted to know if its a good design practice to drive the CE pin of the flip flops using clock signals ?

No, because the global clock nets go only to clock loads and not to a flip-flop's CE pin. You'll get a routing error.
 
You can, however, use logic to drive a BUFG's CE input, so that the clock from that BUFG going to its loads will be enabled as you desire.
----------------------------Yes, I do this for a living.View solution in original post

arvindnr写道：
嘿大家，
快速威廉希尔官方网站 问题：
我一直在阅读有关同步设计实践的一些内容，并试图在我的设计中实现这些想法。
我想知道使用时钟信号驱动触发器的CE引脚是否是一个很好的设计实践？
不，因为全球时钟网仅用于时钟负载而不是触发器的CE引脚。
你会收到路由错误。
但是，您可以使用逻辑来驱动BUFG的CE输入，以便从该BUFG到其负载的时钟将根据您的需要启用。
----------------------------是的，我这样做是为了谋生。



以下为原文

arvindnr wrote:
Hey every one,

Quick technical question :
 
I have been reading a bit about synchronous design practices and trying to implement those ideas in my design. I wanted to know if its a good design practice to drive the CE pin of the flip flops using clock signals ?

No, because the global clock nets go only to clock loads and not to a flip-flop's CE pin. You'll get a routing error.
 
You can, however, use logic to drive a BUFG's CE input, so that the clock from that BUFG going to its loads will be enabled as you desire.
----------------------------Yes, I do this for a living.

嘿，
感谢您的输入。
你的方法似乎更优雅和简单:)我会试一试。
干杯
阿文德



以下为原文

Hey,
 
Thanks for your input. Your method seems to be more eligant and simple :) I will give it a try.

Cheers
Arvind

只是为了澄清。
互连中的资源有限，允许从全局时钟树到包括CE和RST的CLB的输入。
但是你只得到其中的两个，如果你有一个常数0进入CLB，那么就会使用其中一个。
除此之外，在您的情况下，时机将是具有挑战性的。
在BUFGCE上使用CE会好得多。



以下为原文

Just to clarify. There are limited resources in the interconnect that allow inputs from the global clock tree to a CLB including CE and RST. But you only get two of those and if you have a constant 0 going to the CLB then one of the two is used.
 
Other than that, timing would be challenging in you scenario. Much better to use the CE on the BUFGCE.

谢谢你的回复Ralfk，
我正在重新设计模块以使用来自BUFGCE的时钟，并且我从分频器逻辑控制该BUFG的CE引脚。
我刚才遇到了一个挥之不去的问题：我必须用动态划分的Clk驱动我的FIFO在Block RAM中的实现。
我可以通过两种方式做到这一点：
1）使用我的连续快速时钟驱动FIFO的Clk信号，并使用我的BUFGCE输出驱动FIFO的WR和RD使能线。
这样我可以通过打开和关闭BUFGCE以我想要的频率控制读写。
2）第二种方法是使用我的BUFGCE输出直接驱动FIFO时钟输入，并保持WR和RD使能线始终打开。
如果我记得我已经读过，我已经读过FIFO设计通常更喜欢连续时钟，并且必须控制使能线，以便从时钟以较低的频率读取和写入数据。
由于我仍处于模块化VHDL设计阶段，我无法测试我的理论。
有什么输入？



以下为原文

Thanks for your reply Ralfk,
 
I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic. 
 
I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :
 
1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.
 
2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.
 
If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.
 
Since I am still in my modular VHDL design phase I can't test my theory yet.
 
Any inputs ?

arvindnr写道：
谢谢你的回复Ralfk，
我正在重新设计模块以使用来自BUFGCE的时钟，并且我从分频器逻辑控制该BUFG的CE引脚。
我刚才遇到了一个挥之不去的问题：我必须用动态划分的Clk驱动我的FIFO在Block RAM中的实现。
我可以通过两种方式做到这一点：
1）使用我的连续快速时钟驱动FIFO的Clk信号，并使用我的BUFGCE输出驱动FIFO的WR和RD使能线。
这样我可以通过打开和关闭BUFGCE以我想要的频率控制读写。
2）第二种方法是使用我的BUFGCE输出直接驱动FIFO时钟输入，并保持WR和RD使能线始终打开。
我不确定我理解你为什么要这样做。
这是不符合时间的问题吗？
为什么不只是根据需要控制RD和WR信号，分别从RCLK和WCLK运行它们？
如果我记得我已经读过，我已经读过FIFO设计通常更喜欢连续时钟，并且必须控制使能线，以便从时钟以较低的频率读取和写入数据。
FIFO时钟不需要连续，但它有帮助。
它使时序分析更简单，并且由于标志取决于时钟，因此如果时钟停止，您可能看不到标志更改。
将RD校正为真并操纵读取时钟频率比在需要读取时断言RD标志要困难得多。
可以假设您从启用的时钟运行FIFO RCLK然后所有下游逻辑也在该时钟上运行吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

arvindnr wrote:
Thanks for your reply Ralfk,
 
I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic.
 
I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :
 
1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.
 
2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.

I'm not sure I understand why you're trying to do this. Is it a matter of not meeting timing?
 
Why not just control the RD and WR signals as necessary, running them off the RCLK and the WCLK respectively? 

If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.

The FIFO clocks need not be continuous, but it helps. It makes timing analysis simpler and since the flags are dependent on the clock then if the clock stops you might not see a flag change. Tying RD true and manipulating the read clock frequency sounds a lot more difficult than asserting the RD flag when a read is necessary.
 
Can one assume that if you run the FIFO RCLK off of an enabled clock then all of the logic downstream also runs on that clock?
----------------------------Yes, I do this for a living.

对于大多数应用来说，关闭FIFO的时钟通常不是一个好主意，因为你关闭了FIFO中的同步器以及WR / RD指针（计数器），这将导致不可预测的标志行为。
因此，最好让一些逻辑在控制WREN / RDEN的读写时钟上同步运行



以下为原文

Turning the clocks for FIFOs off is generally not a good idea for most applications because you turn off the synchronizers in the FIFO as well as the WR/RD pointers (counters) which would result in unpredictable flag behaviour. So it's best to have some logic running synchronously on the read and write clock which control the WREN/RDEN

bassman59写道：
arvindnr写道：
谢谢你的回复Ralfk，
我正在重新设计模块以使用来自BUFGCE的时钟，并且我从分频器逻辑控制该BUFG的CE引脚。
我刚才遇到了一个挥之不去的问题：我必须用动态划分的Clk驱动我的FIFO在Block RAM中的实现。
我可以通过两种方式做到这一点：
1）使用我的连续快速时钟驱动FIFO的Clk信号，并使用我的BUFGCE输出驱动FIFO的WR和RD使能线。
这样我可以通过打开和关闭BUFGCE以我想要的频率控制读写。
2）第二种方法是使用我的BUFGCE输出直接驱动FIFO时钟输入，并保持WR和RD使能线始终打开。
我不确定我理解你为什么要这样做。
这是不符合时间的问题吗？
为什么不只是根据需要控制RD和WR信号，分别从RCLK和WCLK运行它们？
这不是时间问题。
与主系统100 Mhz时钟相比，我必须以不同的分频将数据写入FIFO。
因此，如果我必须以20 Mhz写入数据，那么我可以每隔5 Mmz时钟周期驱动FIFO的WR使能，或者我可以将我的分频20 Mhz时钟直接连接到FIFO时钟输入并保持Enables为高电平。
这个过程不是连续的，因此时钟不是恒定的。
此外，基于输入动态地改变分频时钟。
这就是另一个因素。
如果我记得我已经读过，我已经读过FIFO设计通常更喜欢连续时钟，并且必须控制使能线，以便从时钟以较低的频率读取和写入数据。
FIFO时钟不需要连续，但它有帮助。
它使时序分析更简单，并且由于标志取决于时钟，因此如果时钟停止，您可能看不到标志更改。
将RD校正为真并操纵读取时钟频率比在需要读取时断言RD标志要困难得多。
可以假设您从启用的时钟运行FIFO RCLK然后所有下游逻辑也在该时钟上运行吗？
我使用通用时钟域fifo设计，因此读写过程与主系统时钟同步。
下游逻辑在主系统时钟上运行。
我将数据从FIFO中锁存出来并稍后使用。
我决定采用你和ralfk建议的任何方式。
与制作时钟本身相比，制作启用线更容易，更好。 
感谢您抽出时间回复。
干杯
阿文德



以下为原文

bassman59 wrote:
arvindnr wrote:
Thanks for your reply Ralfk,
 
I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic.
 
I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :
 
1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.
 
2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.
I'm not sure I understand why you're trying to do this. Is it a matter of not meeting timing?
 
Why not just control the RD and WR signals as necessary, running them off the RCLK and the WCLK respectively? 
 
It is not a problem with timing. I have to Write Data to the FIFO at different divided frequencies compared to my main system 100 Mhz clock. So if I have to write data at say 20 Mhz then I can either drive the WR enable of the FIFO every 5th 100 Mhz clock cycle or I can directly connect my divided 20 Mhz clock to the FIFO clock input and keep the Enables high. This process is not continous and hence the clock is not constant. Also the divided clock is dynamically changed based on inputs. So thats another factor. 

If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.
The FIFO clocks need not be continuous, but it helps. It makes timing analysis simpler and since the flags are dependent on the clock then if the clock stops you might not see a flag change. Tying RD true and manipulating the read clock frequency sounds a lot more difficult than asserting the RD flag when a read is necessary.
 
Can one assume that if you run the FIFO RCLK off of an enabled clock then all of the logic downstream also runs on that clock?
 
I use a common clock domain fifo design so the read and write process is synchronized to the main system clock. The downstream logic runs on the main system clock . I latch the data out from the FIFO and use it later. 
 
Any ways I decided to go with what you and ralfk suggested. Turned out manuplating the Enable lines is more easier and better compared to manuplating the clock's itself. 
 
Thanks for taking out the time to reply.
Cheers
Arvind