完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,
我想知道通过使用c ++代码是否存在使用FPGA资源的肮脏,快速且非常粗糙的想法? 我的任务是在FPGA上实现一个非常复杂的c ++算法。 c ++代码非常复杂,需要几周或几个月才能理解,但同时管理层想知道,例如,如果我的目标是Spartan6,我将拥有多少资源利用率? 我知道这不容易解决,因为它取决于几个因素,例如我使用多少并行进程和其他因素; 但是如果有的话,我可以快速了解一下这会很棒吗? 谢谢, --Rudy 以上来自于谷歌翻译 以下为原文 Hi, I was wondering if there is a dirty, quick and very rough esitmate of using FPGA resources by having a c++ code? My task is to implement a very complicated c++ algorithm on FPGA. the c++ code is very complex and it will take couple weeks or months to understand, but meanwhile the management would like to know, for example if I am targeting an Spartan6, how much resource utilization will I have? I know this cannot be easily addressed, cause it depends on several factors such as how much parallel processes I use and others; but if there is anyway I can get a quick idea that would be great? Thanks, --Rudy |
|
相关推荐
1个回答
|
|
鲁迪,
您的问题的答案就在您的帖子中。 人们必须了解算法需要实现什么,据我所知,这比串行到并行转换器要复杂一些。 几周或几个月了解C ++代码? 谁写这样的代码? 你需要弄清楚的事情包括,但绝对不限于: 1.数据路径宽度与您算法的性质有关 2.每个时钟周期的数学运算 3.工作时钟频率 4.配置参数 - 您需要多少? 接下来,除了算法之外,系统中还有DDR3控制器吗? MicroBlaze的? 高速SERDES? 您的配置如何流入FPGA? 如果这不能回答你的问题,那么别的什么都没有。 干杯弗拉德 弗拉迪斯拉夫·穆拉文 以上来自于谷歌翻译 以下为原文 Rudy, The answer to your question is in your very posting. One has to understand what the algorithm needs to implement, which, as I understand, is a bit more complicated than a serial to parallel converter. Weeks or months to understand C++ code? Who writes such code??? Things you need to figure out include, but definitely not limited to: 1. data path widths as pertaiing to the nature of your algo 2. math operations per clock cycle 3. operating clock frequency 4. configuration parameters - how many do you need? Next, are there any DDR3 controllers in the system in addition to your algo? Microblaze? high-speed SERDES? how your configuration is streamed into the FPGA? If this does not answer your question, nothing else would. Cheers Vlad Vladislav Muravin |
|
|
|
只有小组成员才能发言,加入小组>>
2369 浏览 7 评论
2785 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2253 浏览 9 评论
3328 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2419 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
741浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
529浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
342浏览 1评论
746浏览 0评论
1947浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-13 13:36 , Processed in 1.210310 second(s), Total 78, Slave 62 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号