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我怀疑是否可以在V5和V7器件之间连接LVDS对,两端都是VCCO 1.8V。
V7具有LVDS18标准,但V5仅具有LVDS25。 我仍然可以在V5端使用LVDS25,VCCO用于1.8V的存储体。 谢谢 维沙尔 以上来自于谷歌翻译 以下为原文 i have doubt whether i can connect LVDS pairs between V5 and V7 devices with VCCO 1.8V on both sides. V7 has LVDS18 standard but V5 has only LVDS25. can i still use LVDS25 on V5 side with VCCO for bank being 1.8V. Thanks vishal |
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3个回答
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没有理由不确定。
比较LVDS信号输入和输出电压的V5和V7数据表规范。 V7 LVDS输出是否与V5 LVDS输入兼容? V5 LVDS输出是否与V7 LVDS输入兼容? 您是否能够找到V5和V7设备系列的数据表? V5数据表是Xilinx doc DS202。 LVDS规范见表9。 V7数据表是Xilinx doc DS183。 LVDS规范见表12(HR库)和表13(HP库)。 将LVDS从V5发送到V7或从V7发送到V5没有问题。 在V5器件上,应使用LVDS_25 SelectIO标准,VCCO应为2.5V。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 There is no reason for uncertainty. Compare the V5 and V7 datasheet specifications for LVDS signal input and output voltages. Are V7 LVDS outputs compatible with V5 LVDS inputs? Are V5 LVDS outputs compatible with V7 LVDS inputs? Are you able to locate the datasheets for the V5 and V7 device families? The V5 datasheet is Xilinx doc DS202. LVDS specifications are found in Table 9. The V7 datasheet is Xilinx doc DS183. LVDS specifications are found in Table 12 (HR banks) and Table 13 (HP banks). There is no problem sending LVDS from V5 to V7, or from V7 to V5. On the V5 device, you should use LVDS_25 SelectIO standard and VCCO should be 2.5V. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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LVDS是LVDS是LVDS :-) LVDS上的电压电平不依赖于驱动它的器件的VCCO(只要你能满足最低规格)。
因此,VCCO 1.8V器件可以产生VVDO = 2.5V器件可以接收的LVDS电平(反之亦然)。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 LVDS is LVDS is LVDS :-) The voltage level on LVDS don't depend on the VCCO of the device driving it (as long as you can meet the minimum specs that is). So a VCCO 1.8V device can generate the LVDS levels which a VCOO=2.5V device can receive (and vice versa).- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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Bob和Muzzafer给出的答案是正确的......
但是...... 在FPGA配置完成且I / O变为LVDS之前,它们将被上拉至其bank供电电压(1.8 V和2.5 V)。 这可能很糟糕。 因此,请确保将HSWAPEN或其在V5和V7引脚上调用的任何内容拉到“配置期间的浮动I / O”级别。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 The answers given by Bob and Muzzafer are correct ... HOWEVER ... Until the FPGA configuration is complete and the I/Os become LVDS, they will be pulled up to their bank supply voltages (1.8 V and 2.5 V). This could be bad. So make sure that the HSWAPEN or whatever it's called on V5 and V7 pins are pulled to the "float I/O during configuration" level. ----------------------------Yes, I do this for a living. |
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