如何在IO内部启用触发器？

嗨，
从vivado 2013.1开始，IOB属性可以应用于端口。
端口上的IOB属性仅在端口由单个触发器驱动/驱动时才起作用。
如果有多个翻牌，那么我们需要在翻牌圈明确指定IOB属性，我们希望在IOB中打包。
干杯，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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在原帖中查看解决方案



以下为原文

Hi,
 
Starting from vivado 2013.1, the IOB property can be applied on ports.
 
The IOB property on ports works only if the port is driving/being driven by a single flop. In case if there is more than one flop, then we need to explicitly specify the IOB property on the flop which we would like to get packed in the IOB.
 
Cheers,
Deepika.
Thanks,
Deepika.
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在ISE Navigator图形外壳中，单击灯泡图标。
这将打开语言模板，包括许多编码示例。
在那里，您将找到包含在代码中的属性的用法示例，这些属性将寄存器指向IO块。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

From within the ISE Navigator graphics shell, click on the light-bulb icon.  This brings up the Language Templates, including many coding examples.  In there you will find usage examples for the attributes to include in your code which will direct registers to the IO blocks.
 
-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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buddha1987写道：
我记得在IO库中应该有一个触发器，它直接与引脚连接。
所以我的问题是如何在IO内启用触发器？
有没有Xdc约束可以实现这个功能？
非常感谢。
我使用ISE，所以如果你在Vivado，我无能为力。
可能存在等效约束。
但是在XST中，有一个名为-iob的“Xilinx特定选项”条目，“将I / O寄存器装入IOB”。
默认值为“auto”，这意味着满足XST指南中条件的代码，触发器可能最终在IOB中。
将它设置为“是”并且可以进入IOB的触发器将会出现，而那些不能被标记为警告的触发器（您可以忽略）。
将其设置为“是”。
在ISE中，有一个称为“I / O寄存器/锁存到IOB”的映射约束（-pr b），您应该将其设置为“For Inputs and Outputs”。
----------------------------是的，我这样做是为了谋生。



以下为原文

buddha1987 wrote:
I remember there should be the flip flop inside the IO bank which directly connet with pins. So my question how can I enable the flip flop inside the IO ? Is there any Xdc constrain can achieve this function?
 
Thanks very much.

I use ISE, so if you're in Vivado, I can't help. There are likely equivalent constraints.
 
But In XST' there's a "Xilinx Specific Options" entry called -iob, "Pack I/O Registers into IOBs." The default is "auto," which means that code that meets the criteria in the XST guide, the flops could end up in the IOB. Set it to "yes" and flops that can go in the IOB will, and those that can't will be flagged with a warning (which you can ignore). Set this to "yes."
 
And in ISE, there is a map constraint called "Pack I/O Registers/Latches into IOBs" (-pr b) which you should set to "For Inputs and Outputs." 
----------------------------Yes, I do this for a living.

您好，非常感谢，你们俩。
是的，我使用的是Vivado，所以这是一个小小的区别。我发现这个xdc命令：set_property IOB true [get_cells]我理解的是“寄存器单元”我需要在这个命令中写入我要放在IOB中的寄存器，
对吧？但在我的设计中，这只能是直接连接输入（输出）的第一个（最后一个）寄存器，为什么还需要分配呢？非常感谢。



以下为原文

Hello,

Thanks very much, both of you.

Yes, I use Vivado, so that is a liitle difference.

I found this xdc command:

set_property IOB true [get_cells ]


My understand is the "register cells" I need write in this command is the register I want to put inside the IOB, right?

But in my design, this can only be the first (last) register which connect directly with input (output), why do I still need to assign it?

Thanks very much.

但在我的设计中，这只能是直接连接输入（输出）的第一个（最后一个）寄存器，为什么还需要分配它？
因为MAP模块可以将寄存器放置在FPGA架构而不是IO块中，如果MAP模块认为这将导致更好的性能或更好的封装密度。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

But in my design, this can only be the first (last) register which connect directly with input (output), why do I still need to assign it?
 
Because the MAP module can place the register in the FPGA fabric instead of at the IO Block, if the MAP module believes this will result in better performance or better packing density.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

IOB属性可以直接应用于端口或连接到顶级端口的寄存器。请查看以下链接：http：//www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug912-vivado-properties.pdf in page
47.Thanks。



以下为原文

The IOB property can be applied to either ports or the registers connected to top level port directly.

Check following link:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug912-vivado-properties.pdf in page 47.


Thanks.

嗨，
从vivado 2013.1开始，IOB属性可以应用于端口。
端口上的IOB属性仅在端口由单个触发器驱动/驱动时才起作用。
如果有多个翻牌，那么我们需要在翻牌圈明确指定IOB属性，我们希望在IOB中打包。
干杯，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
Starting from vivado 2013.1, the IOB property can be applied on ports.
 
The IOB property on ports works only if the port is driving/being driven by a single flop. In case if there is more than one flop, then we need to explicitly specify the IOB property on the flop which we would like to get packed in the IOB.
 
Cheers,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

还有一个问题，在我在IOB中启用触发器之后，我仍然需要在Xdc文件中放置正确的输入延迟约束来检查并确保IO时序关闭，对吧？谢谢。



以下为原文

Just one more question, after I enabled the flip flop inside the IOB, I still need to put the proper input delay constrain in Xdc file to check and ensure the IO timing is closed, right?

Thanks.

可能没有。
具体来说，你想解决什么问题？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Probably NO.  What problem, specifically, are you trying to solve?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

所以你的意思是在这种情况下，我甚至不需要输入延迟约束了？不，我没有问题。
我只是假设一个非常非常“极端”的情况，即输入到FPGA的信号不符合建立或保持要求。
但是我在IOB中启用了FF，所以在这种情况下，是否意味着输入时序必须失败？谢谢。



以下为原文

So you mean in this case, I even don't need input delay constrain any more?

No, I did't have a problem. I just assume a very very "extreme" situation that the input signal into the FPGA doesn't meet setup or hold requirements. But I enabled the FF inside the IOB, so in this case, does it mean the input timing MUST fail ?

Thanks.