没有在AXI_DMA Rx端接收到正确的数据

嗨，
我正在使用Zedboard来测试我们的设计。
例如，我们正在尝试使用AXI_DMA，带有AXI接口的FIFO，带有AXI接口的自定义逻辑来建立设计。我们正在尝试执行简单的环回测试。
当我们进行此测试时，我们没有在AXI_DMA Rx端接收到正确的数据。为了验证自定义逻辑工作正常，我已经使用PlanAhed 14.4 / 14.6将chipscope Pro添加到我的设计中。
我们遵循了PlanAhed教程：使用Chipscope -UG677进行调试（v 14.5）以调试此问题。我们发现PlanAhead工具推断出ILA核心的多个实例，因为我们增加了标记为调试的“网络”数量。
有时，32位总线的网络最终会出现在两个不同的ILA内核（每个16位）中。
任何指针？
或者任何人都可以指出我在UISng PA其他UG677上的chipcope pro调试中的任何其他材料。
问候
钱德拉



以下为原文

Hi ,
I'm using Zedboard to test our design. For example we are trying to establish a design using AXI_DMA, FIFO with AXI interface, Custom logic with AXI interface.
We are trying to perform a  simple loop back test. We are not receiving  proper data at the AXI_DMA Rx side when we do this test.

In order to verify  out custom logic is working fine i had go into adding chipscope Pro into my design using PlanAhed 14.4/14.6. We had followed PlanAhed Tutorial : Debugging with Chipscope -UG677 (v 14.5)   in order to debug this issue.

We found that PlanAhead tool infers more than 1 instances of ILA core as we increase the number of "Nets" marked for debug. Sometimes it happens that a Nets which is 32-bit bus could end up in two different ILA cores (16 bit each).

any pointers?  or Can any one point me to a any other  material on chipscope pro debugging in uisng PA other that UG677.

regards
Chandra