zynq自定义ip中的时钟频率是多少？

喜悦，
您的自定义IP具有名为S_AXI_ACLK的端口，现在与IP2BUS_clk相同。现在检查XPS中的.mhs，如果您发现在FCLK_CLK0中端口映射到S_AXI_ACLK（这通常会发生）..那么FCLK_CLK0是您的IP的时钟源。
在Zynq标签的XPS中，点击时钟生成，你会发现FCLK_CLK0的频率......通常为50Mhz ......
我更喜欢使用vivado和IPI进行这种设计......这个端口连接似乎很清楚..
谢谢
在原帖中查看解决方案



以下为原文

Joy,
 
Your custom IP has port called S_AXI_ACLK now this same as IP2BUS_clk..now check the .mhs in XPS, if you find that in FCLK_CLK0 is port mapped to S_AXI_ACLK ( this  usually happens)..Then FCLK_CLK0 is the clock source to your IP. In XPS from Zynq tab,,click on clock generation, you would find the frequncy of FCLK_CLK0..usually 50Mhz...
 
I would prefer to use vivado and IPI for this designs..as this port connections seems to be much clear there..
 
thanks
View solution in original post

表25-1，ug585
可以将AXI总线时钟选择为某些数值。
选择100 MHz，133和200 MHz也是如此。
因此，您选择的时钟和设置将为您提供正在发生的事情......
表25-2列出了所有可用的外设时钟速率，它们是CPU系统时钟的倍数。
25-3列出了例子。
25-10列出了您请求的clcoks。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

table 25-1, ug585
 
The AXI bus clock may be selected to be some number of values.
 
100 MHz is a selection, as are 133, and 200 MHz.
 
So, the clock you choose and the settings, will provide you with what is happening...
 
Table 25-2 lists all the available peripheral clock rates as a multiple  of the system clock for the CPU's.
 
25-3 lists examples.
 
25-10 lists the clcoks you requested.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

喜悦，
您的自定义IP具有名为S_AXI_ACLK的端口，现在与IP2BUS_clk相同。现在检查XPS中的.mhs，如果您发现在FCLK_CLK0中端口映射到S_AXI_ACLK（这通常会发生）..那么FCLK_CLK0是您的IP的时钟源。
在Zynq标签的XPS中，点击时钟生成，你会发现FCLK_CLK0的频率......通常为50Mhz ......
我更喜欢使用vivado和IPI进行这种设计......这个端口连接似乎很清楚..
谢谢



以下为原文

Joy,
 
Your custom IP has port called S_AXI_ACLK now this same as IP2BUS_clk..now check the .mhs in XPS, if you find that in FCLK_CLK0 is port mapped to S_AXI_ACLK ( this  usually happens)..Then FCLK_CLK0 is the clock source to your IP. In XPS from Zynq tab,,click on clock generation, you would find the frequncy of FCLK_CLK0..usually 50Mhz...
 
I would prefer to use vivado and IPI for this designs..as this port connections seems to be much clear there..
 
thanks

嘿
我从你的主题中受到启发，我有一个类似但不同的问题，我已经使用ip pakager设计了一个参数化计数器，现在我创建一个新的系统，我称之为Ip，现在用户更改了参数，即计数器宽度。
现在，因为我将输出作为外部输出，但如何给出时钟和重置以及独立运行用于行为模拟
所以任何解决方案，其次，我需要使用PS部分为我的IP驱动时钟
或者测试台足以运行行为模拟
其次我可以生成一个位文件并在Zedboard上测试该设计，然后如何编写ucf / xdc文件。
请帮助我，我正在努力解决这个问题，从120小时开始



以下为原文

HEY
 
I am inspired from your topic , i Have a similar but different problem , I Have design a parameterised counter using ip pakager now i make a new system where i called that Ip , now user changed parameter i.e. counter width .
 
now since i made output as external but how to give clock and reset and standalone run that for behavioural simulation
 
so any solution to that , secondly do i need to use PS section to drive clock for my IP 
or A test bench is sufficient to run the behavioural simulation 
 
secondly can i generate a bit file and test that design on Zedboard , then how to write the ucf/xdc file.
 
please help me , i am working to resolve such from lasr 120 hours 

你可以给你的设计PDF，这样我们就可以做这样的练习
我们将感激你



以下为原文

can you give your design PDF so we can do such exercise 
we will be grateful to you 

拉夫，
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以下为原文

gaurav,
 
Please do not post multiple copies of your request in multiple threads.  And please do not pose a new question or problem in a thread which has already been marked as 'solved'.
 
Please keep discussion of your issue in the thread you have already created.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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对不起，我将在未来和论坛的礼仪照顾这个



以下为原文

Sorry , I will take care of the this in future and decorum of forum