为FPGA编写Verilog是否需要定义每个状态下的X，Y和Z？

这在综合论坛中是最好的，但我会在这里和你回答你的问题
可以在该论坛中提出进一步的问题。
1）当你在谈论状态机时，我希望你的意思是一个案例陈述。
通常用于时钟进程（1进程状态机）中的case语句
大多数有经验的设计师都喜欢这样做，只需要做出分配就足够了
当寄存器需要改变时。
对于组合过程，你应该做一个
在每种情况下分配，或在案例陈述之前放置默认分配
如果没有任务，处理任何州。
我一般会推荐
远离双进程状态机，但这是你的地方
最有可能陷入困境。
2）当你说编译器时，我假设你的意思是合成器，因为编译器
模拟不会创建可能被“浪费”的硬件。
通常是合成器
很好地优化了它生成的硬件。
结果的任何组合形式
在常数中，除了与地或Vcc的绑定之外，不会创建硬件。
看起来你仍然有很多阅读要做。
我希望你能随意问
你去的时候会有更多问题。
但是我也建议习惯运行
工具，看看你是否可以通过实验回答一些自己的问题。
-  Gabor



以下为原文

This would be best in the Synthesis Forum, but I'll answer your questions here and you
can ask further questions in that forum.
 
1) When you are talking about a state machine, I hope you mean a case statement.
Generally for a case statement within a clocked process (the 1-process state machine
preferred by most experienced designers) it is sufficient to make assigments only
when a register needs to change.  For a combinatorial process you should make an
assignment in each case, or place a default assignment before the case statement
to handle any states were there is no assignment.  I would generally recommend
staying away from the two-process state machine, however as this is where you
are most likely to get into trouble.
 
2) When you say compiler, I assume you mean synthesizer, because the compiler for
simulation doesn't create hardware that might be "wasted."  A synthesizer is generally
quite good a optimizing the hardware it generates.  Any combination form that results
in a constant will not create hardware other than tie-offs to ground or Vcc.
 
It looks like you still have quite a bit of reading to do.  I hope you'll feel free to ask
more questions as you go.  However I'd also suggest getting used to running the
tools to see if you can answer some of your own questions by experimentation.
-- Gabor

我一直致力于我的最后一年项目，该项目基于图像加密的硬件实现，我发现处理图像矩阵的问题。
我尝试过几种方法，但问题仍然存在。
问题是：
我有一个存储在1-D阵列中的图像（256级 - 灰度级）（因为I-VERILOG不支持2-D阵列）。
我需要按特定顺序拍摄一些特定的像素，例如：
@（posedge clk）
开始
M1M2M3
其中k和M1，M2，M3是寄存器数据类型，k在每个时钟脉冲增加。（计数器）
但是在编译时，其中一个错误如下所示：部分选择表达式必须是常量。
这个m***表达式违反了规则：（（'sd24）*（k））+（'sd23）
其他错误消息类似。
我甚至尝试过循环。
但同样的错误仍然存​​在。
选择数组的特定元素范围并将其赋予寄存器的另一种方法是什么？
如果你可以帮助我，我将非常感激。



以下为原文

I've been working on my final year project which is based on hardware implementation of Image Encryption and I am finding a problem dealing with the matrix of the image. I have tried few ways, but the problem still persists.
 The problem is:I have an image (256 level -gray scale) stored in a 1-D Array (as 2-D array is not supported in I-VERILOG). I need to take some particular pixels in a particular order, for example:@(posedge clk)beginM1<=Image[24*k+7:24*k];
M2<=Image[24*k+15:24*k+8];
M3<=Image[24*k+23:24*k+16];end

where k and M1,M2,M3 are register data-type,and k is increasing at every clock pulse.(counter)But on compiling, one of the errors is as shown :
Part select expressions must be constant.
This m*** expression violates the rule: (('sd24)*(k))+('sd23)

The other error messages are similar. I even tried for loop for the same. But the same error persists.What can be the other way to select a particular range of elements of an array and give it to a register? It will be really grateful if you can help me about the same. 

您的代码看起来对我来说是正确的，并且分配了一个恒定的8位值。
哪个工具输出此错误消息？
您能否发布完整的错误消息？
您是否考虑过使用BlockRAM存储数据？
这将大大减少资源量并导致更快的设计。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Your code looks correct to me with a constant 8-bit value assigned. Which tool is outputting this error message? And can you please post the full error message?

Have you considered using a BlockRAM for storing the data ? This will drastically reduced the amount of resources and result in a faster design.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com