[问答]

数据偶尔会存储在2个地址的内存地址中

问答对人有帮助，内容完整，我也想知道答案 0 我有一个数据采集系统，它使用反序列化器同时捕获触发器和数据。当发生触发时，相关数据被存储到存储器中。我遇到的问题是数据通常存储在正确的内存地址中，但它偶尔会存储在2个地址的内存地址中。当FPGA上的温度达到40摄氏度时，我会看到这种行为。我实际上在一台设备上看到40C以下的数据不正确，而在另一台设备上的40C以上。输入时钟被分频以供控制逻辑和真正的双端口存储器使用。我用不同的时钟读出来。输入时钟具有适当的时序约束。我已尝试对数据进行各种OFFSET IN约束并触发以查看是否可以解决问题，但无济于事。我还缺少其他时间限制会对这种行为产生影响吗？这个问题我有点困惑。非常感谢所有的帮助和建议。谢谢，乔纳森以上来自于谷歌翻译以下为原文 I have a data acquisition system that uses deserializers to capture the trigger and the data at the same time. When a trigger occurs, the correlated data is stored into memory. The issue I am having is that the data usually gets stored in the correct memory address, but it will occasionally get stored in a memory address 2 addresses away. I see this behavior when the temperature reaches 40 degrees C on the FPGA. I've actually seen incorrect data below 40C on one device and above 40C on a different device. The input clock is divided by for use by the control logic and the true dual-port memory. I read out using a different clock. The input clocks have appropriate timing constraints. I have tried various OFFSET IN constraints on the data and trigger to see if I could fix the issue, but to no avail. Are there other timing constraints that I am missing that would have an impact on this behavior? I am a bit baffled by this issue. All help and suggestions are very much appreciated. Thanks, Jonathan 0
2019-3-1 11:36:19　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答举报孙缅禧相关推荐 • 使用MPLABX如何找内存地址在哪里 2688 • labview如何获取到图像的内存地址 3802 • 求助，内存地址空间是否一定大于所有物理存储器的容量？ 253 • 请问GATT_Notification函数中是不是有判断发送数据内存地址的机制？ 316 • S5PV210的内存地址线与CPU地址空间有何关系 1047 • 从哪里可以找到ST25DV04k的内存地址大小呢？ 213 • 请问C语言中内存地址是否占用存储空间呢？ 2079 • 如何在AURIX TC375控制器中向DFLASH存储器写入单字节数据？ 297 • PIC16F877A组装如何减去两个存储器地址并将结果存储到第三个地址 1193 • 关于在蜂鸟e203上执行的C语言的内存地址问题 247 1个回答

答案对人有帮助，有参考价值 0 jmhuber写道：我有一个数据采集系统，它使用反序列化器同时捕获触发器和数据。当发生触发时，相关数据被存储到存储器中。我遇到的问题是数据通常存储在正确的内存地址中，但它偶尔会存储在2个地址的内存地址中。当FPGA上的温度达到40摄氏度时，我会看到这种行为。我实际上在一台设备上看到40C以下的数据不正确，而在另一台设备上的40C以上。输入时钟被分频以供控制逻辑和真正的双端口存储器使用。我用不同的时钟读出来。输入时钟具有适当的时序约束。我已尝试对数据进行各种OFFSET IN约束并触发以查看是否可以解决问题，但无济于事。我还缺少其他时间限制会对这种行为产生影响吗？这个问题我有点困惑。非常感谢所有的帮助和建议。谢谢，乔纳森就像数据点一样：我有一个Spartan 6设计，它有多个ADC通过DDR源同步总线连接到它。对ADC的数据执行一些处理，然后将其填充到BRAM乒乓缓冲器中。第九个时钟运行逻辑，该逻辑读取缓冲区并将数据推出另一个DDR源同步缓冲区。没有散热器，FPGA很快就会崩溃。 ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 jmhuber wrote: I have a data acquisition system that uses deserializers to capture the trigger and the data at the same time. When a trigger occurs, the correlated data is stored into memory. The issue I am having is that the data usually gets stored in the correct memory address, but it will occasionally get stored in a memory address 2 addresses away. I see this behavior when the temperature reaches 40 degrees C on the FPGA. I've actually seen incorrect data below 40C on one device and above 40C on a different device. The input clock is divided by for use by the control logic and the true dual-port memory. I read out using a different clock. The input clocks have appropriate timing constraints. I have tried various OFFSET IN constraints on the data and trigger to see if I could fix the issue, but to no avail. Are there other timing constraints that I am missing that would have an impact on this behavior? I am a bit baffled by this issue. All help and suggestions are very much appreciated. Thanks, Jonathan Just as a data point: I have a Spartan 6 design which has multiple ADCs connected to it over DDR source-synchronous buses. Some processing is performed on the ADCs' data, which are then stuffed into BRAM ping-pong buffers. A ninth clock runs the logic which reads the buffers and pushes the data out over another DDR source-synchronous buffer. Without a heat sink the FPGA falls down pretty quickly. ----------------------------Yes, I do this for a living.

2019-3-1 11:47:43 评论举报黄淳