.UCF计时时序约束中只指定对300MHz信号约束

亲爱的大家，
我刚刚进入FPGA设计领域，并在最近几周做了很多阅读。
我相当自信我可以回答我自己的问题，但我只想确认一下。
场景：
我有一个24MHz的时钟
我通过IBUFG将其转换为内部信号
3.我立即使用DCM进行相位同步和PLL这24MHz高达300MHz的信号
我把这个300MHz的信号充电到我的逻辑
我的问题是：
在我的.UCF计时时序约束中，我只指定了对300MHz信号的约束，并假设它将通过DCM / PLL和引脚上升流。
有人可以确认我的简化时序描述的尝试是有效的（因为我对时序约束文档的解释是，只在一个CLK上执行此操作是有效的）。
干杯，
詹姆士



以下为原文

Dear All,

I am just getting into the realm of FPGA design and have done much reading in the recent weeks. I am fairly confident I can answer my own question but I just wanted to confirm.

Scenario:

1. I have an incoming 24MHz clock
2. I translate this to an internal signal via an IBUFG
3. I immediately use a DCM to phase synchronize and PLL this 24MHz up to 300MHz signal
4. I BUFG this 300MHz signal to fan out to my logic

My question is:

In my .UCF timing constraints for clocking, I have ONLY specified the constraint on the 300MHz signal and am assuming that it will ripple up stream through the DCM/PLL and to the pin. Could somebody please confirm that my attempt at simplifying the timing description is valid (as my interpretation of the timing constraints documentation is that yes it is valid to do this on just the one CLK).

Cheers,

James