Spartan 3E XC3S250E中的100Kbit RAM模块使用问题

大家好，
我想在Spartan 3E XC3S250E中使用100Kbits Memrory（6400字深16位宽），根据数据表，它有216Kbits的总RAM（12个RAM块）。数据表还说每个RAM块包含18Kbits的RAM，分为16Kbits
数据存储和分配给奇偶校验的2K位。
我发现在每个RAM块中唯一有用的内存配置是1Kx16（无奇偶校验）。
所以我发现为了使用上面的配置实现100Kbit RAM，我需要使用7个RAM块，
因为只有一个原语（工具 - >语言模板 - >设备预先实例化 - > spartan-3E-> Block RAM->单端口 - > RAMB16_S18），该语言模板支持1Kx16。
我如何使这7个块表现得像一个RAM Block.are有任何基元用于自定义RAM块的长度和深度。
我也尝试过使用Core发生器，但它只支持1K长的RAM移位寄存器。
任何帮助将非常感谢。
谢谢。
PS：我正在使用Xilinx ISE 14.4



以下为原文

Hi All,

I want  to use a 100Kbits Memrory (6400 words Deep  16 bit wide )  in Spartan 3E XC3S250E  which acording to the datasheet has 216Kbits Total RAM(12 RAM blocks).the data sheets also says each RAM block contains 18Kbits of RAM divided into 16Kbits of data storage and 2K bits allocated to parity.
the only memory configuration which i found useful in each RAM Block was 1Kx16 (no parity).
So I have found that in order to implement  100Kbit RAM using the above configuration i need to use 7 RAM blocks,
As there is only one  primitive(tools->language templates->Device premitive instantiation->spartan-3E->Block RAM->Single Port->RAMB16_S18) which is supported by the language template which is for 1Kx16.


how do i make these 7 blocks behave like a single RAM Block.are there any primitives for customising the RAM Blocks length and depth.

I have also tried using the Core generator but it only supports a 1K long RAM shift register.

Any help will be very much appreciated.
Thanks.

PS: i am using Xilinx ISE 14.4