Vivado IP交付

在模拟模型方面，Vivado提供的IP似乎有一些根本性的变化。
在将工作设计从ISE 14.4转换为Vivado 2013.2之后，然后按照建议的方式升级大部分Xilinx IP，例如基本乘法器，除法器，ten_gig_eth_pcs_pma（重量级），看起来像verilog模型现在看来是加密的
VHDL。
例如，自由乘法器12.0核心是加密的VHDL。
根据Vivado用户指南之一，所有Xilinx IP（显然都是免费的IP）是使用IEEE P1735加密标准提供的。它还提到Modelsim PE支持它但是由于我收到这些错误而不清楚...
vcom mult_gen_v12_0.vhd
#Model Technology ModelSim PE vcom 10.2b
＃ - 加载包STANDARD
＃**错误：mult_s10_u16 / mult_gen_v12_0 / simulation / mult_gen_v12_0.vhd（46））：在受保护区域。
＃**错误：mult_gen_v12_0.vhd（46））：在受保护区域。
＃**错误：mult_gen_v12_0.vhd（46））：在受保护区域。
＃**错误：mult_gen_v12_0.vhd（46））：在受保护区域。
＃**错误：mult_gen_v12_0.vhd（46））：在受保护区域。
＃C：/modeltech_pe_10.2b/win32pe/vcom失败了。
我跟着Vivado文档，运行'compile_simlib'等，并使用了Vivado生成的modelsim'do'文件。
我想知道加密模型是否是问题，或者它是modelsim PE（试过10.2b和10.1d）。
导师声称他们应该工作。
使用ISE 14.4中的模型时，所有模拟都可以。
关于我做错了什么或错过什么，或者什么可能被打破的任何想法？
我的观察是否正确，也就是说，现在所有的XilinxIP都是以加密的VHDL形式提供的吗？
我问，因为我正在使用的所有免费的基本核心都是这样生成的。
谢谢，
麦克风



以下为原文

It appears there're some fundamental changes with IP delivered by Vivado in terms of simulation models.  After converting a working design from ISE 14.4 to Vivado 2013.2, then upgrading most of the Xilinx IP as recommended such as basic multipliers, divider, ten_gig_eth_pcs_pma (to name a few), it looks like what had been delivered as verilog models now appear to be encrypted VHDL.  For example, the free multiplier 12.0 core is encrypted VHDL.

According to one of the Vivado User Guides, all Xilinx IP (free IP as well apparently) is delivered using the IEEE P1735 encryption standard. It also mentions that Modelsim PE supports it however that's unclear since I'm getting these errors...

vcom mult_gen_v12_0.vhd
# Model Technology ModelSim PE vcom 10.2b
# -- Loading package STANDARD
# ** Error: mult_s10_u16/mult_gen_v12_0/simulation/mult_gen_v12_0.vhd(46)): in protected region.
# ** Error: mult_gen_v12_0.vhd(46)): in protected region. # ** Error: mult_gen_v12_0.vhd(46)): in protected region.
# ** Error: mult_gen_v12_0.vhd(46)): in protected region. # ** Error:mult_gen_v12_0.vhd(46)): in protected region.
# C:/modeltech_pe_10.2b/win32pe/vcom failed.

I followed all the Vivado docs, ran 'compile_simlib', etc., and have used the Vivado generated modelsim 'do' file.   I'm wondering if the encrypted models are the problem, or if it's modelsim PE (tried both 10.2b and 10.1d).  Mentor claims they should work.  Everything simulated ok when using models from ISE 14.4.

Any ideas on what I'm doing wrong or missing, or what could be broken?  

Are my observations correct, that is, is all Xilinx IP now being delivered as encrypted VHDL?  I ask because all the free, basic cores I'm using are being generated as such.

Thanks,
Mike