完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,所有(仍然无法连接图像……)我目前正在实施一个基于FGPA的USB高速控制器使用一个UB3300(WaveSeHARE模块)。当使用全速(12Mbit)时,一切看起来都很好,但是在高速情况下看起来很奇怪。3300模块使用外部复位线硬复位,然后使用函数控制寄存器逻辑复位,暂停被禁用,OTG寄存器被清除,所有其他位都设置为外围全速。在主机连接时,执行通常的高速协商(并且我有CON)。使用范围,我可以清楚地看到重置,外围啁啾,主机啁啾和终端启用),我们按照ULPI规范配置它。当我收到第一个DATA0包后,安装包,一些奇怪的事情发生(见附图)。我使用FPGA本身来捕获所有的ULPI信号。http://www. alvi.com /ZPUI…0xrxCMdOdditiS1.jpg.DATA0数据包是LIGHT中的10字节(GETSA描述符),但是只有9个是由PHY发送的(LASY CRC字节丢失)。在第一个CRC字节(0xDD)之后,NXT行下降,此时我期望接收RXCMD,但是我得到所有零,这根本没有意义。另外,我好像收到了三个。没有来自PHY的RX错误指示。如果我忽略了包长度,CRC检查并继续进行,这一切似乎都很顺利。然后我从主机中获得In包,并且我可以在没有任何问题的情况下将它发送出去:http://wwwalAlv.com /ZPUI…GES/UB33xIn nAk.jpg2包似乎很受欢迎,有些人不这样做——我有时得到(10字节请求)7字节,8字节,9字节。我似乎从来没有收到任何RxRebug指示。如果我确实有CRC检查,我完全无法枚举该设备在HS -它确实在FS枚举完美,同一PHY。任何线索可能会发生什么?阿尔维
以上来自于百度翻译 以下为原文 Hi all, (still unable to link images...) I am currently implementing a FGPA-based USB High-Speed controller using an USB3300 (Waveshare module). Everything seems to work well when using Full-Speed (12Mbit), but things are looking weird at High-Speed. Just to give a glimpse of the initial setup, the USB3300 module is hard-reset using the external reset line, then logically reset using the Function Control register, Suspend is disabled, OTG register is cleared and all other bits are set up for Peripheral Full-Speed. Upon host connection, the usual High-Speed negotiation is performed (and I have confirmed it using a scope, I can see clearly the reset, Peripheral Chirp, Host Chirp and the terminators enabling) and we configure it as per ULPI spec. When I receive the first DATA0 packet, after the SETUP packet, something odd happens (see attached figure). I have used the FPGA itself to capture all ULPI signals. http://www.alvie.com/zpui...00_rxcmd_oddities1.jpg The DATA0 packet is 10 bytes in lenght (GET_DESCRIPTOR), but only 9 are sent by the PHY (the lasy CRC byte is missing). After the 1st CRC byte (0xDD), the NXT line goes down, and at this point I'd expect to receive an RXCMD, but I get all zeroes, which do not make sense at all. Plus, I seem to receive three of them. There is no RXERROR indication coming from the PHY. If I ignore the packet lenght, the CRC check and proceed, it all seems to go well - I then get the IN packet from the host, and I can NAK it without any issue: http://www.alvie.com/zpui...ges/u***3300_in_nak.jpg Some packets seem to be well received, some others do not - I sometimes get (for a 10-byte request) 7 bytes, 8 bytes, 9 bytes. I never seem to receive any RXERROR indication at all. If I do have the CRC checks in place, I am completely unable to enumerate the device at HS - It does enumerate perfectly at FS, with the same PHY. Any clues about what might be going on ? Alvie |
|
相关推荐
6个回答
|
|
这是设备或主机控制器的实现吗?你如何尊重所需的PHY设置/保持/输出时间?你有一些我能看的逻辑分析仪的踪迹吗?克里斯
以上来自于百度翻译 以下为原文 Is this a device or host controller implementation? How do you honor the required PHY setup/hold/output times? Do you have some logic analyzer trace that I could look at? Chris |
|
|
|
这是外围设备(设备)实现。设置/保持时间由FPGA时序约束保证。请注意,我没有看到任何数据/控制异常可以通过设置/保持定时来解释。根据FPGA POST时序分析,最坏情况设置为1093NS,最坏情况保持为1.73NS,在指定范围内。输出延迟最坏的情况是8052NS。所有这些定时都与PHY输出时钟有关,并且考虑数据+时钟延迟和不确定性。再次注意,在FS中,所有数据+RXCMD都接收到OK。这似乎只发生在HS上。我没有任何逻辑分析仪可以处理这个速度。我捕捉到的波形是由FPGA自己直接采样的。我不明白为什么NXT变为零。这不能由安装/保持计时引起。数据也没有意义(我希望有点翻转,而不是全部零)。只是两个音符:我使用了2个模块,都表现出相同的行为。我已经测试了两个USB主机接口,同样的问题。所描绘的DATA0数据包捕获总是可重复的(虽然在一些测试中,我得到了0x02.0、0x00、0x00作为最后的树字节)。但是我没有尝试过使用完全不同的USB主机(即另一台PC)阿尔瓦罗。
以上来自于百度翻译 以下为原文 This is Peripheral (device) implementation. The setup/hold times are guaranteed by FPGA timing constraints. Note that I do not see any data/control oddities that can be explained by setup/hold timings. According to the FPGA post-PR timing analysis, worst case setup is 10.993ns and worst case hold is 1.743ns, well within specified range. Output delay is worst case 8.052ns. All those timings are relative to the PHY output clock, and account for data+clock delays and uncertainty. Again, note that at FS all data+rxcmd are received OK. This only seem to happen with HS. I don't have any logic analyser that can handle this speed. The waveforms I have "captured" are direcly sampled by the FPGA itself. What I do not understand is why NXT goes to zero. This cannot be caused by setup/hold timings. Data also does not make sense (I'd expect some bit flips, not all zeroes). Just a couple of notes: I used 2 modules, both exhibit same behaviour. I have tested two USB host interfaces, same issue. The depicted DATA0 packet capture is always reproducible (although in some tests I got 0x02,0x00,0x00 as the last tree bytes). What I have not tried was to use a completely different USB host (i.e., another PC) Alvaro |
|
|
|
我不相信像ChipScope这样的“内部”LAS,而是直接查看信号。你不必花一大笔钱来进行:HTTP://PC.TestTo仪。COM/它有一个小的示例缓冲区,但它是一个复杂的触发器,可以调试微风。WaveSHARE S500 E板和他们的3300个PHY模块,在我知道如何读取和写入PHY寄存器之后,其他所有的东西都是RaReTrimvial.Irc,我没有看到像你们这样的任何奇怪的响应,所以这就是我要做的:-从几个“已知的好”寄存器中写入/读取,例如,它们的POR值-用LA或快速范围的接口信号来验证电层。&再次注意,在FS中,所有数据+RXCMD都可以接受。这似乎只发生在HS身上,这是非常可能的。请记住,USB高速的速度是全速的40倍。您可能还希望确保设备侧电容在规格限制内,见附件JPG。这都是关于浪涌电流限制的,而在下游有较大的去耦上限的情况下,我也会给出它。注意,希望这有帮助!克里斯
以上来自于百度翻译 以下为原文 I would not trust some "internal" LAs like ChipScope, rather look at the signals directly. You don't have to spend a fortune to get going: http://www.pctestinstruments.com/ It has a small sample buffer BUT a sophisticated trigger which makes debugging a breeze. My device implementation used one of the WaveShare S500E boards and their 3300 PHY module, and after I figured out how to read and write to the PHY registers, everything else was rather trivial. IIRC, I didn't see any of these strange responses like you did, so this is what I would do: - write to / read from several "known-good" registers, e.g. their POR values - look at the interface signals with a LA or fast scope to verify the electrical layer. > Again, note that at FS all data+rxcmd are received OK. This only seem to happen with HS. Very much possible. Remember that USB Hi-Speed is a whopping 40 times as fast as Full-Speed. You may also want to make sure the device-side capacitance is within spec limits, see attached jpg. This is all about inrush current limiting, and while it may work OK with larger decoupling caps downstream, I would also give it some attention. Hope this helps! Chris Attached Image(s) |
|
|
|
我的设备实现使用了WaveShaysS500 E板和他们的3300个PHY模块,在我知道如何读取和写入PHY寄存器之后,其他一切都是非常琐碎的。你们使用HS还是FS?非常可能。记住,USB高速的速度是全速的40倍,不是真的。PHY接口仍然以相同的速度运行(60MHz)。不同的是,当你收到一个数据八位字节和一堆RXCMD,当你在FS工作的时候。我已经确认了数据使用相同的FPGA设计(与HS协商禁用),一切看起来…好的。我可以捕获FS GETH DeXrTror事务,并在这里发布(稍后要做),通过断言NXT而不发布RXCMD,该模块看起来不像ULPI规范。现在,我想知道为什么会发生这种情况……电源问题?阿尔维
以上来自于百度翻译 以下为原文 > My device implementation used one of the WaveShare S500E boards and their 3300 PHY module, and after I figured out how to read and write to the PHY registers, everything else was rather trivial. Were you using HS or FS ? > Very much possible. Remember that USB Hi-Speed is a whopping 40 times as fast as Full-Speed. Not really. The PHY interface still runs at same speed (60Mhz). The difference is mostly when receiving you get a DATA octet, and a bunch of RXCMD from the PHY when working at FS. I have confirmed the data using the same FPGA design (with HS negotiaition disabled) and everything looks.. OK. I can capture an FS GET_DESCTRIPTOR transaction and post here (will have to do it later though) By de-asserting NXT and not issuing an RXCMD the module looks like not compiant with ULPI spec. Now, I wonder why this is happening... Power supply issues ? Alvie |
|
|
|
你是用HS还是FS?我唯一的建议是重复我自己:你认为你得到的数据可能不是你在ULPI界面上看到的数据。然而,这些FPGA内部的LAS确实有其正当性。克里斯
以上来自于百度翻译 以下为原文 > Were you using HS or FS ? Hi-Speed only. I am afraid the only advice I can offer is to repeat myself: The data you think you get might not be what you actually see on the ULPI interface. Nonetheless - these FPGA-internal LAs sure have their justification. Chris |
|
|
|
嗨,你有没有通过微芯片检查你的原理图?有一个免费的服务叫做USBcheck,有人会审查你的示意图和布局,然后回来一个广泛的报告…你会惊讶的质量;=)如果你不使用这项服务,我建议你做…HS设计需要仔细做。张贴机票,并选择“检查服务”。在门票和附加示意+ GeBeress + LayouTrGARDS
以上来自于百度翻译 以下为原文 Hi, Did you get your schematic reviewed by Microchip ? There is a free service called USBcheck and someone will review your schematic & layout and come back with an extensive report...you'll be surprised of the quality ;=) If you did not use this service I suggest you do...HS design need to be done carefully. Post a ticket and select "Check Services" in the ticket and attach schemtic + gerbers + layout Regards |
|
|
|
只有小组成员才能发言,加入小组>>
5370 浏览 9 评论
2100 浏览 8 评论
2004 浏览 10 评论
请问是否能把一个ADC值转换成两个字节用来设置PWM占空比?
3277 浏览 3 评论
请问电源和晶体值之间有什么关系吗?PIC在正常条件下运行4MHz需要多少电压?
2312 浏览 5 评论
879浏览 1评论
768浏览 1评论
有偿咨询,关于MPLAB X IPE烧录PIC32MX所遇到的问题
706浏览 1评论
PIC Kit3出现目标设备ID(00000000)与预期的设备ID(02c20000)不匹配。是什么原因
764浏览 0评论
653浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2025-3-6 23:22 , Processed in 1.107363 second(s), Total 55, Slave 49 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191